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* [PULL 00/41] tcg patch queue
@ 2020-01-08  3:44 Richard Henderson
  2020-01-08  3:44 ` [PULL 01/41] configure: Drop adjustment of textseg Richard Henderson
                   ` (41 more replies)
  0 siblings, 42 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell

The following changes since commit 035eed4c0d257c905a556fa0f4865a0c077b4e7f:

  Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request' into staging (2020-01-07 17:08:21 +0000)

are available in the Git repository at:

  https://github.com/rth7680/qemu.git tags/pull-tcg-20200108

for you to fetch changes up to 5e7ef51cbe47e726f76bfbc208e167085cf398c4:

  MAINTAINERS: Replace Claudio Fontana for tcg/aarch64 (2020-01-08 11:54:12 +1100)

----------------------------------------------------------------
Improve -static and -pie linking
Add cpu_{ld,st}*_mmuidx_ra
Remove MMU_MODE*_SUFFIX
Move tcg headers under include/

----------------------------------------------------------------
Philippe Mathieu-Daudé (4):
      tcg: Search includes from the project root source directory
      tcg: Search includes in the parent source directory
      tcg: Move TCG headers to include/tcg/
      configure: Remove tcg/ from the preprocessor include search list

Richard Henderson (37):
      configure: Drop adjustment of textseg
      tcg: Remove softmmu code_gen_buffer fixed address
      configure: Do not force pie=no for non-x86
      configure: Always detect -no-pie toolchain support
      configure: Unnest detection of -z,relro and -z,now
      configure: Override the os default with --disable-pie
      configure: Support -static-pie if requested
      target/xtensa: Use probe_access for itlb_hit_test
      cputlb: Use trace_mem_get_info instead of trace_mem_build_info
      trace: Remove trace_mem_build_info_no_se_[bl]e
      target/s390x: Include tcg.h in mem_helper.c
      target/arm: Include tcg.h in sve_helper.c
      accel/tcg: Include tcg.h in tcg-runtime.c
      linux-user: Include tcg.h in syscall.c
      linux-user: Include trace-root.h in syscall-trace.h
      plugins: Include trace/mem.h in api.c
      cputlb: Move body of cpu_ldst_template.h out of line
      translator: Use cpu_ld*_code instead of open-coding
      cputlb: Rename helper_ret_ld*_cmmu to cpu_ld*_code
      cputlb: Provide cpu_(ld,st}*_mmuidx_ra for user-only
      target/i386: Use cpu_*_mmuidx_ra instead of templates
      cputlb: Expand cpu_ldst_useronly_template.h in user-exec.c
      target/nios2: Remove MMU_MODE{0,1}_SUFFIX
      target/alpha: Remove MMU_MODE{0,1}_SUFFIX
      target/cris: Remove MMU_MODE{0,1}_SUFFIX
      target/i386: Remove MMU_MODE{0,1,2}_SUFFIX
      target/microblaze: Remove MMU_MODE{0,1,2}_SUFFIX
      target/sh4: Remove MMU_MODE{0,1}_SUFFIX
      target/unicore32: Remove MMU_MODE{0,1}_SUFFIX
      target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX
      target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0,1}_SUFFIX
      target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
      target/s390x: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
      target/ppc: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
      cputlb: Remove support for MMU_MODE*_SUFFIX
      cputlb: Expand cpu_ldst_template.h in cputlb.c
      MAINTAINERS: Replace Claudio Fontana for tcg/aarch64

 Makefile                                  |   2 +-
 accel/tcg/atomic_template.h               |  67 ++---
 include/exec/cpu_ldst.h                   | 446 +++++++++---------------------
 include/exec/cpu_ldst_template.h          | 211 --------------
 include/exec/cpu_ldst_useronly_template.h | 159 -----------
 include/exec/translator.h                 |  48 +---
 {tcg => include/tcg}/tcg-gvec-desc.h      |   0
 {tcg => include/tcg}/tcg-mo.h             |   0
 {tcg => include/tcg}/tcg-op-gvec.h        |   0
 {tcg => include/tcg}/tcg-op.h             |   2 +-
 {tcg => include/tcg}/tcg-opc.h            |   0
 {tcg => include/tcg}/tcg.h                |  33 +--
 include/user/syscall-trace.h              |   2 +
 target/alpha/cpu.h                        |   2 -
 target/cris/cpu.h                         |   2 -
 target/i386/cpu.h                         |   3 -
 target/m68k/cpu.h                         |   2 -
 target/microblaze/cpu.h                   |   3 -
 target/mips/cpu.h                         |   4 -
 target/nios2/cpu.h                        |   2 -
 target/ppc/cpu.h                          |   2 -
 target/s390x/cpu.h                        |   5 -
 target/sh4/cpu.h                          |   2 -
 target/unicore32/cpu.h                    |   2 -
 target/xtensa/cpu.h                       |   4 -
 tcg/i386/tcg-target.h                     |   2 +-
 trace/mem-internal.h                      |  17 --
 accel/tcg/cpu-exec.c                      |   2 +-
 accel/tcg/cputlb.c                        | 315 ++++++++++++++++-----
 accel/tcg/tcg-runtime-gvec.c              |   2 +-
 accel/tcg/tcg-runtime.c                   |   1 +
 accel/tcg/translate-all.c                 |  39 +--
 accel/tcg/user-exec.c                     | 238 +++++++++++++++-
 bsd-user/main.c                           |   2 +-
 cpus.c                                    |   2 +-
 exec.c                                    |   2 +-
 linux-user/main.c                         |   2 +-
 linux-user/syscall.c                      |   1 +
 plugins/api.c                             |   1 +
 target/alpha/translate.c                  |   2 +-
 target/arm/helper-a64.c                   |   2 +-
 target/arm/sve_helper.c                   |   1 +
 target/arm/translate-a64.c                |   4 +-
 target/arm/translate-sve.c                |   6 +-
 target/arm/translate.c                    |   4 +-
 target/cris/translate.c                   |   2 +-
 target/hppa/translate.c                   |   2 +-
 target/i386/mem_helper.c                  |   2 +-
 target/i386/seg_helper.c                  |  56 ++--
 target/i386/translate.c                   |   2 +-
 target/lm32/translate.c                   |   2 +-
 target/m68k/op_helper.c                   |  77 ++++--
 target/m68k/translate.c                   |   2 +-
 target/microblaze/translate.c             |   2 +-
 target/mips/op_helper.c                   | 182 ++++--------
 target/mips/translate.c                   |   2 +-
 target/moxie/translate.c                  |   2 +-
 target/nios2/translate.c                  |   2 +-
 target/openrisc/translate.c               |   2 +-
 target/ppc/mem_helper.c                   |  13 +-
 target/ppc/translate.c                    |   4 +-
 target/riscv/cpu_helper.c                 |   2 +-
 target/riscv/translate.c                  |   2 +-
 target/s390x/mem_helper.c                 |  11 +-
 target/s390x/translate.c                  |   4 +-
 target/sh4/translate.c                    |   2 +-
 target/sparc/ldst_helper.c                |   2 +-
 target/sparc/translate.c                  |   2 +-
 target/tilegx/translate.c                 |   2 +-
 target/tricore/translate.c                |   2 +-
 target/unicore32/translate.c              |   2 +-
 target/xtensa/mmu_helper.c                |   5 +-
 target/xtensa/translate.c                 |   2 +-
 tcg/aarch64/tcg-target.inc.c              |   4 +-
 tcg/arm/tcg-target.inc.c                  |   4 +-
 tcg/i386/tcg-target.inc.c                 |   4 +-
 tcg/mips/tcg-target.inc.c                 |   2 +-
 tcg/optimize.c                            |   2 +-
 tcg/ppc/tcg-target.inc.c                  |   4 +-
 tcg/riscv/tcg-target.inc.c                |   4 +-
 tcg/s390/tcg-target.inc.c                 |   4 +-
 tcg/sparc/tcg-target.inc.c                |   2 +-
 tcg/tcg-common.c                          |   2 +-
 tcg/tcg-op-gvec.c                         |   8 +-
 tcg/tcg-op-vec.c                          |   6 +-
 tcg/tcg-op.c                              |   6 +-
 tcg/tcg.c                                 |   2 +-
 tcg/tci.c                                 |   2 +-
 MAINTAINERS                               |   4 +-
 configure                                 | 117 +++-----
 docs/devel/loads-stores.rst               | 215 ++++++++++----
 91 files changed, 1075 insertions(+), 1357 deletions(-)
 delete mode 100644 include/exec/cpu_ldst_template.h
 delete mode 100644 include/exec/cpu_ldst_useronly_template.h
 rename {tcg => include/tcg}/tcg-gvec-desc.h (100%)
 rename {tcg => include/tcg}/tcg-mo.h (100%)
 rename {tcg => include/tcg}/tcg-op-gvec.h (100%)
 rename {tcg => include/tcg}/tcg-op.h (99%)
 rename {tcg => include/tcg}/tcg-opc.h (100%)
 rename {tcg => include/tcg}/tcg.h (96%)


^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 01/41] configure: Drop adjustment of textseg
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 02/41] tcg: Remove softmmu code_gen_buffer fixed address Richard Henderson
                   ` (40 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, Thomas Huth, Alex Bennée

This adjustment was random and unnecessary.  The user mode
startup code in probe_guest_base() will choose a value for
guest_base that allows the host qemu binary to not conflict
with the guest binary.

With modern distributions, this isn't even used, as the default
is PIE, which does the same job in a more portable way.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Remove mention of config-host.ld from make distclean
---
 Makefile  |  2 +-
 configure | 47 -----------------------------------------------
 2 files changed, 1 insertion(+), 48 deletions(-)

diff --git a/Makefile b/Makefile
index 6b5ad1121b..95809ec455 100644
--- a/Makefile
+++ b/Makefile
@@ -727,7 +727,7 @@ rm -f $(MANUAL_BUILDDIR)/$1/objects.inv $(MANUAL_BUILDDIR)/$1/searchindex.js $(M
 endef
 
 distclean: clean
-	rm -f config-host.mak config-host.h* config-host.ld $(DOCS) qemu-options.texi qemu-img-cmds.texi qemu-monitor.texi qemu-monitor-info.texi
+	rm -f config-host.mak config-host.h* $(DOCS) qemu-options.texi qemu-img-cmds.texi qemu-monitor.texi qemu-monitor-info.texi
 	rm -f tests/tcg/config-*.mak
 	rm -f config-all-devices.mak config-all-disas.mak config.status
 	rm -f $(SUBDIR_DEVICES_MAK)
diff --git a/configure b/configure
index 0ce2c0354a..0f365bfdf1 100755
--- a/configure
+++ b/configure
@@ -6308,49 +6308,6 @@ if test "$cpu" = "s390x" ; then
   fi
 fi
 
-# Probe for the need for relocating the user-only binary.
-if ( [ "$linux_user" = yes ] || [ "$bsd_user" = yes ] ) && [ "$pie" = no ]; then
-  textseg_addr=
-  case "$cpu" in
-    arm | i386 | ppc* | s390* | sparc* | x86_64 | x32)
-      # ??? Rationale for choosing this address
-      textseg_addr=0x60000000
-      ;;
-    mips)
-      # A 256M aligned address, high in the address space, with enough
-      # room for the code_gen_buffer above it before the stack.
-      textseg_addr=0x60000000
-      ;;
-  esac
-  if [ -n "$textseg_addr" ]; then
-    cat > $TMPC <<EOF
-    int main(void) { return 0; }
-EOF
-    textseg_ldflags="-Wl,-Ttext-segment=$textseg_addr"
-    if ! compile_prog "" "$textseg_ldflags"; then
-      # In case ld does not support -Ttext-segment, edit the default linker
-      # script via sed to set the .text start addr.  This is needed on FreeBSD
-      # at least.
-      if ! $ld --verbose >/dev/null 2>&1; then
-        error_exit \
-            "We need to link the QEMU user mode binaries at a" \
-            "specific text address. Unfortunately your linker" \
-            "doesn't support either the -Ttext-segment option or" \
-            "printing the default linker script with --verbose." \
-            "If you don't want the user mode binaries, pass the" \
-            "--disable-user option to configure."
-      fi
-
-      $ld --verbose | sed \
-        -e '1,/==================================================/d' \
-        -e '/==================================================/,$d' \
-        -e "s/[.] = [0-9a-fx]* [+] SIZEOF_HEADERS/. = $textseg_addr + SIZEOF_HEADERS/" \
-        -e "s/__executable_start = [0-9a-fx]*/__executable_start = $textseg_addr/" > config-host.ld
-      textseg_ldflags="-Wl,-T../config-host.ld"
-    fi
-  fi
-fi
-
 # Check that the C++ compiler exists and works with the C compiler.
 # All the QEMU_CXXFLAGS are based on QEMU_CFLAGS. Keep this at the end to don't miss any other that could be added.
 if has $cxx; then
@@ -7905,10 +7862,6 @@ if test "$gprof" = "yes" ; then
   fi
 fi
 
-if test "$target_linux_user" = "yes" || test "$target_bsd_user" = "yes" ; then
-  ldflags="$ldflags $textseg_ldflags"
-fi
-
 # Newer kernels on s390 check for an S390_PGSTE program header and
 # enable the pgste page table extensions in that case. This makes
 # the vm.allocate_pgste sysctl unnecessary. We enable this program
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 02/41] tcg: Remove softmmu code_gen_buffer fixed address
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
  2020-01-08  3:44 ` [PULL 01/41] configure: Drop adjustment of textseg Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 03/41] configure: Do not force pie=no for non-x86 Richard Henderson
                   ` (39 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, Thomas Huth, Alex Bennée

The commentary talks about "in concert with the addresses
assigned in the relevant linker script", except there is no
linker script for softmmu, nor has there been for some time.

(Do not confuse the user-only linker script editing that was
removed in the previous patch, because user-only does not
use this code_gen_buffer allocation method.)

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/translate-all.c | 37 +++++--------------------------------
 1 file changed, 5 insertions(+), 32 deletions(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index bb325a2bc4..7749c3dda5 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1032,47 +1032,20 @@ static inline void *alloc_code_gen_buffer(void)
 {
     int prot = PROT_WRITE | PROT_READ | PROT_EXEC;
     int flags = MAP_PRIVATE | MAP_ANONYMOUS;
-    uintptr_t start = 0;
     size_t size = tcg_ctx->code_gen_buffer_size;
     void *buf;
 
-    /* Constrain the position of the buffer based on the host cpu.
-       Note that these addresses are chosen in concert with the
-       addresses assigned in the relevant linker script file.  */
-# if defined(__PIE__) || defined(__PIC__)
-    /* Don't bother setting a preferred location if we're building
-       a position-independent executable.  We're more likely to get
-       an address near the main executable if we let the kernel
-       choose the address.  */
-# elif defined(__x86_64__) && defined(MAP_32BIT)
-    /* Force the memory down into low memory with the executable.
-       Leave the choice of exact location with the kernel.  */
-    flags |= MAP_32BIT;
-    /* Cannot expect to map more than 800MB in low memory.  */
-    if (size > 800u * 1024 * 1024) {
-        tcg_ctx->code_gen_buffer_size = size = 800u * 1024 * 1024;
-    }
-# elif defined(__sparc__)
-    start = 0x40000000ul;
-# elif defined(__s390x__)
-    start = 0x90000000ul;
-# elif defined(__mips__)
-#  if _MIPS_SIM == _ABI64
-    start = 0x128000000ul;
-#  else
-    start = 0x08000000ul;
-#  endif
-# endif
-
-    buf = mmap((void *)start, size, prot, flags, -1, 0);
+    buf = mmap(NULL, size, prot, flags, -1, 0);
     if (buf == MAP_FAILED) {
         return NULL;
     }
 
 #ifdef __mips__
     if (cross_256mb(buf, size)) {
-        /* Try again, with the original still mapped, to avoid re-acquiring
-           that 256mb crossing.  This time don't specify an address.  */
+        /*
+         * Try again, with the original still mapped, to avoid re-acquiring
+         * the same 256mb crossing.
+         */
         size_t size2;
         void *buf2 = mmap(NULL, size, prot, flags, -1, 0);
         switch ((int)(buf2 != MAP_FAILED)) {
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 03/41] configure: Do not force pie=no for non-x86
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
  2020-01-08  3:44 ` [PULL 01/41] configure: Drop adjustment of textseg Richard Henderson
  2020-01-08  3:44 ` [PULL 02/41] tcg: Remove softmmu code_gen_buffer fixed address Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 04/41] configure: Always detect -no-pie toolchain support Richard Henderson
                   ` (38 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Philippe Mathieu-Daudé

PIE is supported on many other hosts besides x86.

The default for non-x86 is now the same as x86: pie is used
if supported, and may be forced via --enable/--disable-pie.

The original commit (40d6444e91c) said:

  "Non-x86 are not changed, as they require TCG changes"

but I think that's wrong -- there's nothing about PIE that
affects TCG one way or another.

Tested on aarch64 (bionic) and ppc64le (centos 7) hosts.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configure | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/configure b/configure
index 0f365bfdf1..351e39795b 100755
--- a/configure
+++ b/configure
@@ -2019,16 +2019,6 @@ if ! compile_prog "-Werror" "" ; then
 	"Thread-Local Storage (TLS). Please upgrade to a version that does."
 fi
 
-if test "$pie" = ""; then
-  case "$cpu-$targetos" in
-    i386-Linux|x86_64-Linux|x32-Linux|i386-OpenBSD|x86_64-OpenBSD)
-      ;;
-    *)
-      pie="no"
-      ;;
-  esac
-fi
-
 if test "$pie" != "no" ; then
   cat > $TMPC << EOF
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 04/41] configure: Always detect -no-pie toolchain support
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (2 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 03/41] configure: Do not force pie=no for non-x86 Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 05/41] configure: Unnest detection of -z,relro and -z,now Richard Henderson
                   ` (37 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, Thomas Huth, Philippe Mathieu-Daudé

The CFLAGS_NOPIE and LDFLAGS_NOPIE variables are used
in pc-bios/optionrom/Makefile, which has nothing to do
with the PIE setting of the main qemu executables.

This overrides any operating system default to build
all executables as PIE, which is important for ROMs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configure | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/configure b/configure
index 351e39795b..f5248f86cd 100755
--- a/configure
+++ b/configure
@@ -2019,26 +2019,24 @@ if ! compile_prog "-Werror" "" ; then
 	"Thread-Local Storage (TLS). Please upgrade to a version that does."
 fi
 
-if test "$pie" != "no" ; then
-  cat > $TMPC << EOF
+cat > $TMPC << EOF
 
 #ifdef __linux__
 #  define THREAD __thread
 #else
 #  define THREAD
 #endif
-
 static THREAD int tls_var;
-
 int main(void) { return tls_var; }
-
 EOF
-  # check we support --no-pie first...
-  if compile_prog "-Werror -fno-pie" "-no-pie"; then
-    CFLAGS_NOPIE="-fno-pie"
-    LDFLAGS_NOPIE="-nopie"
-  fi
 
+# Check we support --no-pie first; we will need this for building ROMs.
+if compile_prog "-Werror -fno-pie" "-no-pie"; then
+  CFLAGS_NOPIE="-fno-pie"
+  LDFLAGS_NOPIE="-no-pie"
+fi
+
+if test "$pie" != "no" ; then
   if compile_prog "-fPIE -DPIE" "-pie"; then
     QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
     LDFLAGS="-pie $LDFLAGS"
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 05/41] configure: Unnest detection of -z,relro and -z,now
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (3 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 04/41] configure: Always detect -no-pie toolchain support Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 06/41] configure: Override the os default with --disable-pie Richard Henderson
                   ` (36 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Fangrui Song, Alex Bennée,
	Philippe Mathieu-Daudé

There is nothing about these options that is related to PIE.
Use them unconditionally.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Fangrui Song <i@maskray.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Do not split into two tests.
---
 configure | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/configure b/configure
index f5248f86cd..1dd12edcc3 100755
--- a/configure
+++ b/configure
@@ -2041,9 +2041,6 @@ if test "$pie" != "no" ; then
     QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
     LDFLAGS="-pie $LDFLAGS"
     pie="yes"
-    if compile_prog "" "-Wl,-z,relro -Wl,-z,now" ; then
-      LDFLAGS="-Wl,-z,relro -Wl,-z,now $LDFLAGS"
-    fi
   else
     if test "$pie" = "yes"; then
       error_exit "PIE not available due to missing toolchain support"
@@ -2054,6 +2051,12 @@ if test "$pie" != "no" ; then
   fi
 fi
 
+# Detect support for PT_GNU_RELRO + DT_BIND_NOW.
+# The combination is known as "full relro", because .got.plt is read-only too.
+if compile_prog "" "-Wl,-z,relro -Wl,-z,now" ; then
+  LDFLAGS="-Wl,-z,relro -Wl,-z,now $LDFLAGS"
+fi
+
 ##########################################
 # __sync_fetch_and_and requires at least -march=i486. Many toolchains
 # use i686 as default anyway, but for those that don't, an explicit
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 06/41] configure: Override the os default with --disable-pie
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (4 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 05/41] configure: Unnest detection of -z,relro and -z,now Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 07/41] configure: Support -static-pie if requested Richard Henderson
                   ` (35 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Thomas Huth, Alex Bennée,
	Philippe Mathieu-Daudé

Some distributions, e.g. Ubuntu 19.10, enable PIE by default.
If for some reason one wishes to build a non-pie binary, we
must provide additional options to override.

At the same time, reorg the code to an elif chain.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configure | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/configure b/configure
index 1dd12edcc3..de2c4867ad 100755
--- a/configure
+++ b/configure
@@ -2036,19 +2036,18 @@ if compile_prog "-Werror -fno-pie" "-no-pie"; then
   LDFLAGS_NOPIE="-no-pie"
 fi
 
-if test "$pie" != "no" ; then
-  if compile_prog "-fPIE -DPIE" "-pie"; then
-    QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
-    LDFLAGS="-pie $LDFLAGS"
-    pie="yes"
-  else
-    if test "$pie" = "yes"; then
-      error_exit "PIE not available due to missing toolchain support"
-    else
-      echo "Disabling PIE due to missing toolchain support"
-      pie="no"
-    fi
-  fi
+if test "$pie" = "no"; then
+  QEMU_CFLAGS="$CFLAGS_NOPIE $QEMU_CFLAGS"
+  LDFLAGS="$LDFLAGS_NOPIE $LDFLAGS"
+elif compile_prog "-fPIE -DPIE" "-pie"; then
+  QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
+  LDFLAGS="-pie $LDFLAGS"
+  pie="yes"
+elif test "$pie" = "yes"; then
+  error_exit "PIE not available due to missing toolchain support"
+else
+  echo "Disabling PIE due to missing toolchain support"
+  pie="no"
 fi
 
 # Detect support for PT_GNU_RELRO + DT_BIND_NOW.
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 07/41] configure: Support -static-pie if requested
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (5 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 06/41] configure: Override the os default with --disable-pie Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 08/41] target/xtensa: Use probe_access for itlb_hit_test Richard Henderson
                   ` (34 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, Alex Bennée

Recent toolchains support static and pie at the same time.

As with normal dynamic builds, allow --static to default to PIE
if supported by the toolchain.  Allow --enable/--disable-pie to
override the default.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix --disable-pie --static
---
 configure | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/configure b/configure
index de2c4867ad..94a4b1c848 100755
--- a/configure
+++ b/configure
@@ -1025,7 +1025,6 @@ for opt do
   ;;
   --static)
     static="yes"
-    LDFLAGS="-static $LDFLAGS"
     QEMU_PKG_CONFIG_FLAGS="--static $QEMU_PKG_CONFIG_FLAGS"
   ;;
   --mandir=*) mandir="$optarg"
@@ -2001,11 +2000,6 @@ if test "$static" = "yes" ; then
   if test "$modules" = "yes" ; then
     error_exit "static and modules are mutually incompatible"
   fi
-  if test "$pie" = "yes" ; then
-    error_exit "static and pie are mutually incompatible"
-  else
-    pie="no"
-  fi
 fi
 
 # Unconditional check for compiler __thread support
@@ -2036,7 +2030,18 @@ if compile_prog "-Werror -fno-pie" "-no-pie"; then
   LDFLAGS_NOPIE="-no-pie"
 fi
 
-if test "$pie" = "no"; then
+if test "$static" = "yes"; then
+  if test "$pie" != "no" && compile_prog "-fPIE -DPIE" "-static-pie"; then
+    QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS"
+    LDFLAGS="-static-pie $LDFLAGS"
+    pie="yes"
+  elif test "$pie" = "yes"; then
+    error_exit "-static-pie not available due to missing toolchain support"
+  else
+    LDFLAGS="-static $LDFLAGS"
+    pie="no"
+  fi
+elif test "$pie" = "no"; then
   QEMU_CFLAGS="$CFLAGS_NOPIE $QEMU_CFLAGS"
   LDFLAGS="$LDFLAGS_NOPIE $LDFLAGS"
 elif compile_prog "-fPIE -DPIE" "-pie"; then
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 08/41] target/xtensa: Use probe_access for itlb_hit_test
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (6 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 07/41] configure: Support -static-pie if requested Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 09/41] cputlb: Use trace_mem_get_info instead of trace_mem_build_info Richard Henderson
                   ` (33 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Max Filippov

We don't actually need the result of the read, only to probe that the
memory mapping exists.  This is exactly what probe_access does.

This is also the only user of any cpu_ld*_code_ra function.
Removing this allows the interface to be removed shortly.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/xtensa/mmu_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index f15bff306f..b01ff9399a 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -63,10 +63,11 @@
 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
 {
     /*
-     * Attempt the memory load; we don't care about the result but
+     * Probe the memory; we don't care about the result but
      * only the side-effects (ie any MMU or other exception)
      */
-    cpu_ldub_code_ra(env, vaddr, GETPC());
+    probe_access(env, vaddr, 1, MMU_INST_FETCH,
+                 cpu_mmu_index(env, true), GETPC());
 }
 
 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 09/41] cputlb: Use trace_mem_get_info instead of trace_mem_build_info
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (7 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 08/41] target/xtensa: Use probe_access for itlb_hit_test Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 10/41] trace: Remove trace_mem_build_info_no_se_[bl]e Richard Henderson
                   ` (32 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

In the cpu_ldst templates, we already require a MemOp, and it
is cleaner and clearer to pass that instead of 3 separate
arguments describing the memory operation.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst_template.h          | 22 +++++++++++-----------
 include/exec/cpu_ldst_useronly_template.h | 12 ++++++------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
index 54b5e858ce..0ad5de3ef9 100644
--- a/include/exec/cpu_ldst_template.h
+++ b/include/exec/cpu_ldst_template.h
@@ -86,9 +86,9 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
     RES_TYPE res;
     target_ulong addr;
     int mmu_idx = CPU_MMU_INDEX;
-    TCGMemOpIdx oi;
+    MemOp op = MO_TE | SHIFT;
 #if !defined(SOFTMMU_CODE_ACCESS)
-    uint16_t meminfo = trace_mem_build_info(SHIFT, false, MO_TE, false, mmu_idx);
+    uint16_t meminfo = trace_mem_get_info(op, mmu_idx, false);
     trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
 #endif
 
@@ -96,9 +96,9 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
     entry = tlb_entry(env, mmu_idx, addr);
     if (unlikely(entry->ADDR_READ !=
                  (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
-        oi = make_memop_idx(SHIFT, mmu_idx);
+        TCGMemOpIdx oi = make_memop_idx(op, mmu_idx);
         res = glue(glue(helper_ret_ld, URETSUFFIX), MMUSUFFIX)(env, addr,
-                                                            oi, retaddr);
+                                                               oi, retaddr);
     } else {
         uintptr_t hostaddr = addr + entry->addend;
         res = glue(glue(ld, USUFFIX), _p)((uint8_t *)hostaddr);
@@ -125,9 +125,9 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
     int res;
     target_ulong addr;
     int mmu_idx = CPU_MMU_INDEX;
-    TCGMemOpIdx oi;
-#if !defined(SOFTMMU_CODE_ACCESS)
-    uint16_t meminfo = trace_mem_build_info(SHIFT, true, MO_TE, false, mmu_idx);
+    MemOp op = MO_TE | MO_SIGN | SHIFT;
+#ifndef SOFTMMU_CODE_ACCESS
+    uint16_t meminfo = trace_mem_get_info(op, mmu_idx, false);
     trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
 #endif
 
@@ -135,7 +135,7 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
     entry = tlb_entry(env, mmu_idx, addr);
     if (unlikely(entry->ADDR_READ !=
                  (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
-        oi = make_memop_idx(SHIFT, mmu_idx);
+        TCGMemOpIdx oi = make_memop_idx(op & ~MO_SIGN, mmu_idx);
         res = (DATA_STYPE)glue(glue(helper_ret_ld, SRETSUFFIX),
                                MMUSUFFIX)(env, addr, oi, retaddr);
     } else {
@@ -167,9 +167,9 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
     CPUTLBEntry *entry;
     target_ulong addr;
     int mmu_idx = CPU_MMU_INDEX;
-    TCGMemOpIdx oi;
+    MemOp op = MO_TE | SHIFT;
 #if !defined(SOFTMMU_CODE_ACCESS)
-    uint16_t meminfo = trace_mem_build_info(SHIFT, false, MO_TE, true, mmu_idx);
+    uint16_t meminfo = trace_mem_get_info(op, mmu_idx, true);
     trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
 #endif
 
@@ -177,7 +177,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
     entry = tlb_entry(env, mmu_idx, addr);
     if (unlikely(tlb_addr_write(entry) !=
                  (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
-        oi = make_memop_idx(SHIFT, mmu_idx);
+        TCGMemOpIdx oi = make_memop_idx(op, mmu_idx);
         glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi,
                                                      retaddr);
     } else {
diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h
index dbdc7a845d..e5a3d1983a 100644
--- a/include/exec/cpu_ldst_useronly_template.h
+++ b/include/exec/cpu_ldst_useronly_template.h
@@ -70,8 +70,8 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
     ret = glue(glue(ld, USUFFIX), _p)(g2h(ptr));
     clear_helper_retaddr();
 #else
-    uint16_t meminfo = trace_mem_build_info(SHIFT, false, MO_TE, false,
-                                            MMU_USER_IDX);
+    MemOp op = MO_TE | SHIFT;
+    uint16_t meminfo = trace_mem_get_info(op, MMU_USER_IDX, false);
     trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
     ret = glue(glue(ld, USUFFIX), _p)(g2h(ptr));
 #endif
@@ -102,8 +102,8 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
     ret = glue(glue(lds, SUFFIX), _p)(g2h(ptr));
     clear_helper_retaddr();
 #else
-    uint16_t meminfo = trace_mem_build_info(SHIFT, true, MO_TE, false,
-                                            MMU_USER_IDX);
+    MemOp op = MO_TE | MO_SIGN | SHIFT;
+    uint16_t meminfo = trace_mem_get_info(op, MMU_USER_IDX, false);
     trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
     ret = glue(glue(lds, SUFFIX), _p)(g2h(ptr));
     qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
@@ -131,8 +131,8 @@ static inline void
 glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr,
                                       RES_TYPE v)
 {
-    uint16_t meminfo = trace_mem_build_info(SHIFT, false, MO_TE, true,
-                                            MMU_USER_IDX);
+    MemOp op = MO_TE | SHIFT;
+    uint16_t meminfo = trace_mem_get_info(op, MMU_USER_IDX, true);
     trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
     glue(glue(st, SUFFIX), _p)(g2h(ptr), v);
     qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 10/41] trace: Remove trace_mem_build_info_no_se_[bl]e
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (8 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 09/41] cputlb: Use trace_mem_get_info instead of trace_mem_build_info Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 11/41] target/s390x: Include tcg.h in mem_helper.c Richard Henderson
                   ` (31 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

It is easy for the atomic helpers to use trace_mem_build_info
directly, without resorting to symbol pasting.  For this usage,
we cannot use trace_mem_get_info, because the MemOp does not
support 16-byte accesses.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/atomic_template.h | 67 +++++++++++++------------------------
 trace/mem-internal.h        | 17 ----------
 2 files changed, 24 insertions(+), 60 deletions(-)

diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 837676231f..26969487d6 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -64,13 +64,10 @@
    the ATOMIC_NAME macro, and redefined below.  */
 #if DATA_SIZE == 1
 # define END
-# define MEND _be /* either le or be would be fine */
 #elif defined(HOST_WORDS_BIGENDIAN)
 # define END  _be
-# define MEND _be
 #else
 # define END  _le
-# define MEND _le
 #endif
 
 ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
@@ -79,8 +76,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     DATA_TYPE ret;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
-                                                           ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, 0, false,
+                                         ATOMIC_MMU_IDX);
 
     atomic_trace_rmw_pre(env, addr, info);
 #if DATA_SIZE == 16
@@ -99,8 +96,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
-                                                           ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, 0, false,
+                                         ATOMIC_MMU_IDX);
 
     atomic_trace_ld_pre(env, addr, info);
     val = atomic16_read(haddr);
@@ -114,8 +111,8 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true,
-                                                          ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, 0, true,
+                                         ATOMIC_MMU_IDX);
 
     atomic_trace_st_pre(env, addr, info);
     atomic16_set(haddr, val);
@@ -130,8 +127,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     DATA_TYPE ret;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
-                                                          ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, 0, false,
+                                         ATOMIC_MMU_IDX);
 
     atomic_trace_rmw_pre(env, addr, info);
     ret = atomic_xchg__nocheck(haddr, val);
@@ -147,10 +144,8 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                           \
     DATA_TYPE ret;                                                  \
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
-                                                           false,   \
-                                                           ATOMIC_MMU_IDX); \
-                                                                    \
+    uint16_t info = trace_mem_build_info(SHIFT, false, 0, false,    \
+                                         ATOMIC_MMU_IDX);           \
     atomic_trace_rmw_pre(env, addr, info);                          \
     ret = atomic_##X(haddr, val);                                   \
     ATOMIC_MMU_CLEANUP;                                             \
@@ -183,10 +178,8 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                          \
     XDATA_TYPE cmp, old, new, val = xval;                           \
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
-                                                           false,   \
-                                                           ATOMIC_MMU_IDX); \
-                                                                    \
+    uint16_t info = trace_mem_build_info(SHIFT, false, 0, false,    \
+                                         ATOMIC_MMU_IDX);           \
     atomic_trace_rmw_pre(env, addr, info);                          \
     smp_mb();                                                       \
     cmp = atomic_read__nocheck(haddr);                              \
@@ -213,7 +206,6 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX,  DATA_TYPE, new)
 #endif /* DATA SIZE >= 16 */
 
 #undef END
-#undef MEND
 
 #if DATA_SIZE > 1
 
@@ -221,10 +213,8 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX,  DATA_TYPE, new)
    within the ATOMIC_NAME macro.  */
 #ifdef HOST_WORDS_BIGENDIAN
 # define END  _le
-# define MEND _le
 #else
 # define END  _be
-# define MEND _be
 #endif
 
 ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
@@ -233,9 +223,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     DATA_TYPE ret;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
-                                                           false,
-                                                           ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, false,
+                                         ATOMIC_MMU_IDX);
 
     atomic_trace_rmw_pre(env, addr, info);
 #if DATA_SIZE == 16
@@ -254,9 +243,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
-                                                           false,
-                                                           ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, false,
+                                         ATOMIC_MMU_IDX);
 
     atomic_trace_ld_pre(env, addr, info);
     val = atomic16_read(haddr);
@@ -270,9 +258,8 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
-                                                           true,
-                                                           ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, true,
+                                         ATOMIC_MMU_IDX);
 
     val = BSWAP(val);
     atomic_trace_st_pre(env, addr, info);
@@ -289,9 +276,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     ABI_TYPE ret;
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
-                                                           false,
-                                                           ATOMIC_MMU_IDX);
+    uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP, false,
+                                         ATOMIC_MMU_IDX);
 
     atomic_trace_rmw_pre(env, addr, info);
     ret = atomic_xchg__nocheck(haddr, BSWAP(val));
@@ -307,10 +293,8 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                           \
     DATA_TYPE ret;                                                  \
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
-                                                           false,   \
-                                                           ATOMIC_MMU_IDX); \
-                                                                    \
+    uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP,    \
+                                         false, ATOMIC_MMU_IDX);    \
     atomic_trace_rmw_pre(env, addr, info);                          \
     ret = atomic_##X(haddr, BSWAP(val));                            \
     ATOMIC_MMU_CLEANUP;                                             \
@@ -341,10 +325,8 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                          \
     XDATA_TYPE ldo, ldn, old, new, val = xval;                      \
-    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
-                                                           false,   \
-                                                           ATOMIC_MMU_IDX); \
-                                                                    \
+    uint16_t info = trace_mem_build_info(SHIFT, false, MO_BSWAP,    \
+                                         false, ATOMIC_MMU_IDX);    \
     atomic_trace_rmw_pre(env, addr, info);                          \
     smp_mb();                                                       \
     ldn = atomic_read__nocheck(haddr);                              \
@@ -378,7 +360,6 @@ GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new)
 #endif /* DATA_SIZE >= 16 */
 
 #undef END
-#undef MEND
 #endif /* DATA_SIZE > 1 */
 
 #undef BSWAP
diff --git a/trace/mem-internal.h b/trace/mem-internal.h
index 0a32aa22ca..8b72b678fa 100644
--- a/trace/mem-internal.h
+++ b/trace/mem-internal.h
@@ -47,21 +47,4 @@ static inline uint16_t trace_mem_get_info(MemOp op,
                                 mmu_idx);
 }
 
-/* Used by the atomic helpers */
-static inline
-uint16_t trace_mem_build_info_no_se_be(int size_shift, bool store,
-                                       TCGMemOpIdx oi)
-{
-    return trace_mem_build_info(size_shift, false, MO_BE, store,
-                                get_mmuidx(oi));
-}
-
-static inline
-uint16_t trace_mem_build_info_no_se_le(int size_shift, bool store,
-                                       TCGMemOpIdx oi)
-{
-    return trace_mem_build_info(size_shift, false, MO_LE, store,
-                                get_mmuidx(oi));
-}
-
 #endif /* TRACE__MEM_INTERNAL_H */
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 11/41] target/s390x: Include tcg.h in mem_helper.c
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (9 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 10/41] trace: Remove trace_mem_build_info_no_se_[bl]e Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 12/41] target/arm: Include tcg.h in sve_helper.c Richard Henderson
                   ` (30 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	David Hildenbrand

Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/s390x/mem_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 2921419c27..20a84b3912 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -27,6 +27,7 @@
 #include "exec/cpu_ldst.h"
 #include "qemu/int128.h"
 #include "qemu/atomic128.h"
+#include "tcg.h"
 
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/s390x/storage-keys.h"
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 12/41] target/arm: Include tcg.h in sve_helper.c
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (10 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 11/41] target/s390x: Include tcg.h in mem_helper.c Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 13/41] accel/tcg: Include tcg.h in tcg-runtime.c Richard Henderson
                   ` (29 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.

Cc: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/sve_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index fc0c1755d2..83cc7f5bb5 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -25,6 +25,7 @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "fpu/softfloat.h"
+#include "tcg.h"
 
 
 /* Note that vector data is stored in host-endian 64-bit chunks,
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 13/41] accel/tcg: Include tcg.h in tcg-runtime.c
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (11 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 12/41] target/arm: Include tcg.h in sve_helper.c Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 14/41] linux-user: Include tcg.h in syscall.c Richard Henderson
                   ` (28 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/tcg-runtime.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 8a1e408e31..4ab2cf7f75 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -30,6 +30,7 @@
 #include "exec/tb-lookup.h"
 #include "disas/disas.h"
 #include "exec/log.h"
+#include "tcg.h"
 
 /* 32-bit helpers */
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 14/41] linux-user: Include tcg.h in syscall.c
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (12 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 13/41] accel/tcg: Include tcg.h in tcg-runtime.c Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 15/41] linux-user: Include trace-root.h in syscall-trace.h Richard Henderson
                   ` (27 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

Code movement in an upcoming patch will show that this file
was implicitly depending on tcg.h being included indirectly.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 linux-user/syscall.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 171c0caef3..34825f15bf 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -115,6 +115,7 @@
 #include "user/syscall-trace.h"
 #include "qapi/error.h"
 #include "fd-trans.h"
+#include "tcg.h"
 
 #ifndef CLONE_IO
 #define CLONE_IO                0x80000000      /* Clone io context */
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 15/41] linux-user: Include trace-root.h in syscall-trace.h
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (13 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 14/41] linux-user: Include tcg.h in syscall.c Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 16/41] plugins: Include trace/mem.h in api.c Richard Henderson
                   ` (26 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

Code movement in an upcoming patch will show that this file
was implicitly depending on trace-root.h being included beforehand.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/user/syscall-trace.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/user/syscall-trace.h b/include/user/syscall-trace.h
index 9e60473643..79fd3e5aa9 100644
--- a/include/user/syscall-trace.h
+++ b/include/user/syscall-trace.h
@@ -10,6 +10,8 @@
 #ifndef _SYSCALL_TRACE_H_
 #define _SYSCALL_TRACE_H_
 
+#include "trace-root.h"
+
 /*
  * These helpers just provide a common place for the various
  * subsystems that want to track syscalls to put their hooks in. We
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 16/41] plugins: Include trace/mem.h in api.c
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (14 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 15/41] linux-user: Include trace-root.h in syscall-trace.h Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:44 ` [PULL 17/41] cputlb: Move body of cpu_ldst_template.h out of line Richard Henderson
                   ` (25 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

Code movement in an upcoming patch will show that this file
was implicitly depending on trace/mem.h being included beforehand.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 plugins/api.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/plugins/api.c b/plugins/api.c
index fa1d9f276d..53c8a73582 100644
--- a/plugins/api.c
+++ b/plugins/api.c
@@ -46,6 +46,7 @@
 #include "qemu/plugin-memory.h"
 #include "hw/boards.h"
 #endif
+#include "trace/mem.h"
 
 /* Uninstall and Reset handlers */
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 17/41] cputlb: Move body of cpu_ldst_template.h out of line
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (15 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 16/41] plugins: Include trace/mem.h in api.c Richard Henderson
@ 2020-01-08  3:44 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 18/41] translator: Use cpu_ld*_code instead of open-coding Richard Henderson
                   ` (24 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:44 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé

With the tracing hooks, the inline functions are no longer
so simple.  Once out-of-line, the current tlb_entry lookup
is redundant with the one in the main load/store_helper.

This also begins the introduction of a new target facing
interface, with suffix *_mmuidx_ra.  This is not yet
official because the interface is not done for user-only.

Use abi_ptr instead of target_ulong in preparation for
user-only; the two types are identical for softmmu.

What remains in cpu_ldst_template.h are the expansions
for _code, _data, and MMU_MODE<N>_SUFFIX.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h          |  25 ++++++-
 include/exec/cpu_ldst_template.h | 125 +++++++------------------------
 accel/tcg/cputlb.c               | 116 ++++++++++++++++++++++++++++
 3 files changed, 166 insertions(+), 100 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index fd499f7e2f..cf8af36dbc 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -152,7 +152,7 @@ static inline void clear_helper_retaddr(void)
 
 #else
 
-/* The memory helpers for tcg-generated code need tcg_target_long etc.  */
+/* Needed for TCG_OVERSIZED_GUEST */
 #include "tcg.h"
 
 static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
@@ -185,6 +185,29 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
     return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
 }
 
+uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                            int mmu_idx, uintptr_t ra);
+uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                            int mmu_idx, uintptr_t ra);
+uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                           int mmu_idx, uintptr_t ra);
+uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                           int mmu_idx, uintptr_t ra);
+
+int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                       int mmu_idx, uintptr_t ra);
+int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                       int mmu_idx, uintptr_t ra);
+
+void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+                       int mmu_idx, uintptr_t retaddr);
+void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+                       int mmu_idx, uintptr_t retaddr);
+void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+                       int mmu_idx, uintptr_t retaddr);
+void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
+                       int mmu_idx, uintptr_t retaddr);
+
 #ifdef MMU_MODE0_SUFFIX
 #define CPU_MMU_INDEX 0
 #define MEMSUFFIX MMU_MODE0_SUFFIX
diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
index 0ad5de3ef9..ea39e29c19 100644
--- a/include/exec/cpu_ldst_template.h
+++ b/include/exec/cpu_ldst_template.h
@@ -24,13 +24,6 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#if !defined(SOFTMMU_CODE_ACCESS)
-#include "trace-root.h"
-#endif
-
-#include "qemu/plugin.h"
-#include "trace/mem.h"
-
 #if DATA_SIZE == 8
 #define SUFFIX q
 #define USUFFIX q
@@ -63,56 +56,40 @@
 #define RES_TYPE uint32_t
 #endif
 
+/* generic load/store macros */
+
 #ifdef SOFTMMU_CODE_ACCESS
-#define ADDR_READ addr_code
-#define MMUSUFFIX _cmmu
-#define URETSUFFIX USUFFIX
-#define SRETSUFFIX glue(s, SUFFIX)
-#else
-#define ADDR_READ addr_read
-#define MMUSUFFIX _mmu
-#define URETSUFFIX USUFFIX
-#define SRETSUFFIX glue(s, SUFFIX)
+
+static inline RES_TYPE
+glue(glue(cpu_ld, USUFFIX), _code)(CPUArchState *env, target_ulong ptr)
+{
+    TCGMemOpIdx oi = make_memop_idx(MO_TE | SHIFT, CPU_MMU_INDEX);
+    return glue(glue(helper_ret_ld, USUFFIX), _cmmu)(env, ptr, oi, 0);
+}
+
+#if DATA_SIZE <= 2
+static inline int
+glue(glue(cpu_lds, SUFFIX), _code)(CPUArchState *env, target_ulong ptr)
+{
+    return (DATA_STYPE)glue(glue(cpu_ld, USUFFIX), _code)(env, ptr);
+}
 #endif
 
-/* generic load/store macros */
+#else
 
 static inline RES_TYPE
 glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
                                                   target_ulong ptr,
                                                   uintptr_t retaddr)
 {
-    CPUTLBEntry *entry;
-    RES_TYPE res;
-    target_ulong addr;
-    int mmu_idx = CPU_MMU_INDEX;
-    MemOp op = MO_TE | SHIFT;
-#if !defined(SOFTMMU_CODE_ACCESS)
-    uint16_t meminfo = trace_mem_get_info(op, mmu_idx, false);
-    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
-#endif
-
-    addr = ptr;
-    entry = tlb_entry(env, mmu_idx, addr);
-    if (unlikely(entry->ADDR_READ !=
-                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
-        TCGMemOpIdx oi = make_memop_idx(op, mmu_idx);
-        res = glue(glue(helper_ret_ld, URETSUFFIX), MMUSUFFIX)(env, addr,
-                                                               oi, retaddr);
-    } else {
-        uintptr_t hostaddr = addr + entry->addend;
-        res = glue(glue(ld, USUFFIX), _p)((uint8_t *)hostaddr);
-    }
-#ifndef SOFTMMU_CODE_ACCESS
-    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
-#endif
-    return res;
+    return glue(glue(cpu_ld, USUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX,
+                                                   retaddr);
 }
 
 static inline RES_TYPE
 glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
 {
-    return glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(env, ptr, 0);
+    return glue(glue(cpu_ld, USUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX, 0);
 }
 
 #if DATA_SIZE <= 2
@@ -121,42 +98,17 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
                                                   target_ulong ptr,
                                                   uintptr_t retaddr)
 {
-    CPUTLBEntry *entry;
-    int res;
-    target_ulong addr;
-    int mmu_idx = CPU_MMU_INDEX;
-    MemOp op = MO_TE | MO_SIGN | SHIFT;
-#ifndef SOFTMMU_CODE_ACCESS
-    uint16_t meminfo = trace_mem_get_info(op, mmu_idx, false);
-    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
-#endif
-
-    addr = ptr;
-    entry = tlb_entry(env, mmu_idx, addr);
-    if (unlikely(entry->ADDR_READ !=
-                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
-        TCGMemOpIdx oi = make_memop_idx(op & ~MO_SIGN, mmu_idx);
-        res = (DATA_STYPE)glue(glue(helper_ret_ld, SRETSUFFIX),
-                               MMUSUFFIX)(env, addr, oi, retaddr);
-    } else {
-        uintptr_t hostaddr = addr + entry->addend;
-        res = glue(glue(lds, SUFFIX), _p)((uint8_t *)hostaddr);
-    }
-#ifndef SOFTMMU_CODE_ACCESS
-    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
-#endif
-    return res;
+    return glue(glue(cpu_lds, SUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX,
+                                                   retaddr);
 }
 
 static inline int
 glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
 {
-    return glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(env, ptr, 0);
+    return glue(glue(cpu_lds, SUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX, 0);
 }
 #endif
 
-#ifndef SOFTMMU_CODE_ACCESS
-
 /* generic store macro */
 
 static inline void
@@ -164,36 +116,15 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
                                                  target_ulong ptr,
                                                  RES_TYPE v, uintptr_t retaddr)
 {
-    CPUTLBEntry *entry;
-    target_ulong addr;
-    int mmu_idx = CPU_MMU_INDEX;
-    MemOp op = MO_TE | SHIFT;
-#if !defined(SOFTMMU_CODE_ACCESS)
-    uint16_t meminfo = trace_mem_get_info(op, mmu_idx, true);
-    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
-#endif
-
-    addr = ptr;
-    entry = tlb_entry(env, mmu_idx, addr);
-    if (unlikely(tlb_addr_write(entry) !=
-                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
-        TCGMemOpIdx oi = make_memop_idx(op, mmu_idx);
-        glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi,
-                                                     retaddr);
-    } else {
-        uintptr_t hostaddr = addr + entry->addend;
-        glue(glue(st, SUFFIX), _p)((uint8_t *)hostaddr, v);
-    }
-#ifndef SOFTMMU_CODE_ACCESS
-    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
-#endif
+    glue(glue(cpu_st, SUFFIX), _mmuidx_ra)(env, ptr, v, CPU_MMU_INDEX,
+                                           retaddr);
 }
 
 static inline void
 glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
                                       RES_TYPE v)
 {
-    glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(env, ptr, v, 0);
+    glue(glue(cpu_st, SUFFIX), _mmuidx_ra)(env, ptr, v, CPU_MMU_INDEX, 0);
 }
 
 #endif /* !SOFTMMU_CODE_ACCESS */
@@ -204,8 +135,4 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
 #undef SUFFIX
 #undef USUFFIX
 #undef DATA_SIZE
-#undef MMUSUFFIX
-#undef ADDR_READ
-#undef URETSUFFIX
-#undef SRETSUFFIX
 #undef SHIFT
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 98221948d6..ddd19718bf 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -34,6 +34,9 @@
 #include "qemu/atomic.h"
 #include "qemu/atomic128.h"
 #include "translate-all.h"
+#include "trace-root.h"
+#include "qemu/plugin.h"
+#include "trace/mem.h"
 #ifdef CONFIG_PLUGIN
 #include "qemu/plugin-memory.h"
 #endif
@@ -1625,6 +1628,75 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
     return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
 }
 
+/*
+ * Load helpers for cpu_ldst.h.
+ */
+
+static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
+                                       int mmu_idx, uintptr_t retaddr,
+                                       MemOp op, FullLoadHelper *full_load)
+{
+    uint16_t meminfo;
+    TCGMemOpIdx oi;
+    uint64_t ret;
+
+    meminfo = trace_mem_get_info(op, mmu_idx, false);
+    trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
+
+    op &= ~MO_SIGN;
+    oi = make_memop_idx(op, mmu_idx);
+    ret = full_load(env, addr, oi, retaddr);
+
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
+
+    return ret;
+}
+
+uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                            int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_UB, full_ldub_mmu);
+}
+
+int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                       int mmu_idx, uintptr_t ra)
+{
+    return (int8_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_SB,
+                                   full_ldub_mmu);
+}
+
+uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                            int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUW,
+                           MO_TE == MO_LE
+                           ? full_le_lduw_mmu : full_be_lduw_mmu);
+}
+
+int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                       int mmu_idx, uintptr_t ra)
+{
+    return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_TESW,
+                                    MO_TE == MO_LE
+                                    ? full_le_lduw_mmu : full_be_lduw_mmu);
+}
+
+uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                           int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEUL,
+                           MO_TE == MO_LE
+                           ? full_le_ldul_mmu : full_be_ldul_mmu);
+}
+
+uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                           int mmu_idx, uintptr_t ra)
+{
+    return cpu_load_helper(env, addr, mmu_idx, ra, MO_TEQ,
+                           MO_TE == MO_LE
+                           ? helper_le_ldq_mmu : helper_be_ldq_mmu);
+}
+
 /*
  * Store Helpers
  */
@@ -1854,6 +1926,50 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
     store_helper(env, addr, val, oi, retaddr, MO_BEQ);
 }
 
+/*
+ * Store Helpers for cpu_ldst.h
+ */
+
+static inline void QEMU_ALWAYS_INLINE
+cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
+                 int mmu_idx, uintptr_t retaddr, MemOp op)
+{
+    TCGMemOpIdx oi;
+    uint16_t meminfo;
+
+    meminfo = trace_mem_get_info(op, mmu_idx, true);
+    trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
+
+    oi = make_memop_idx(op, mmu_idx);
+    store_helper(env, addr, val, oi, retaddr, op);
+
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
+}
+
+void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
+                       int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
+}
+
+void cpu_stw_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
+                       int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUW);
+}
+
+void cpu_stl_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
+                       int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEUL);
+}
+
+void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
+                       int mmu_idx, uintptr_t retaddr)
+{
+    cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEQ);
+}
+
 /* First set of helpers allows passing in of OI and RETADDR.  This makes
    them callable from other helpers.  */
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 18/41] translator: Use cpu_ld*_code instead of open-coding
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (16 preceding siblings ...)
  2020-01-08  3:44 ` [PULL 17/41] cputlb: Move body of cpu_ldst_template.h out of line Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 19/41] cputlb: Rename helper_ret_ld*_cmmu to cpu_ld*_code Richard Henderson
                   ` (23 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

The DO_LOAD macros replicate the distinction already performed
by the cpu_ldst.h functions.  Use them.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h   | 11 ---------
 include/exec/translator.h | 48 +++++++++++----------------------------
 2 files changed, 13 insertions(+), 46 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index cf8af36dbc..399ff6c3da 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -129,11 +129,6 @@ static inline void clear_helper_retaddr(void)
 #include "exec/cpu_ldst_useronly_template.h"
 #undef MEMSUFFIX
 
-/*
- * Code access is deprecated in favour of translator_ld* functions
- * (see translator.h). However there are still users that need to
- * converted so for now these stay.
- */
 #define MEMSUFFIX _code
 #define CODE_ACCESS
 #define DATA_SIZE 1
@@ -455,12 +450,6 @@ void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
 #undef CPU_MMU_INDEX
 #undef MEMSUFFIX
 
-/*
- * Code access is deprecated in favour of translator_ld* functions
- * (see translator.h). However there are still users that need to
- * converted so for now these stay.
- */
-
 #define CPU_MMU_INDEX (cpu_mmu_index(env, true))
 #define MEMSUFFIX _code
 #define SOFTMMU_CODE_ACCESS
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 459dd72aab..638e1529c5 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -148,41 +148,19 @@ void translator_loop_temp_check(DisasContextBase *db);
 /*
  * Translator Load Functions
  *
- * These are intended to replace the old cpu_ld*_code functions and
- * are mandatory for front-ends that have been migrated to the common
- * translator_loop. These functions are only intended to be called
- * from the translation stage and should not be called from helper
- * functions. Those functions should be converted to encode the
- * relevant information at translation time.
+ * These are intended to replace the direct usage of the cpu_ld*_code
+ * functions and are mandatory for front-ends that have been migrated
+ * to the common translator_loop. These functions are only intended
+ * to be called from the translation stage and should not be called
+ * from helper functions. Those functions should be converted to encode
+ * the relevant information at translation time.
  */
 
-#ifdef CONFIG_USER_ONLY
-
-#define DO_LOAD(type, name, shift)               \
-    do {                                         \
-        set_helper_retaddr(1);                   \
-        ret = name ## _p(g2h(pc));               \
-        clear_helper_retaddr();                  \
-    } while (0)
-
-#else
-
-#define DO_LOAD(type, name, shift)                          \
-    do {                                                    \
-        int mmu_idx = cpu_mmu_index(env, true);             \
-        TCGMemOpIdx oi = make_memop_idx(shift, mmu_idx);    \
-        ret = helper_ret_ ## name ## _cmmu(env, pc, oi, 0); \
-    } while (0)
-
-#endif
-
-#define GEN_TRANSLATOR_LD(fullname, name, type, shift, swap_fn)         \
+#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn)             \
     static inline type                                                  \
     fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap)      \
     {                                                                   \
-        type ret;                                                       \
-        DO_LOAD(type, name, shift);                                     \
-                                                                        \
+        type ret = load_fn(env, pc);                                    \
         if (do_swap) {                                                  \
             ret = swap_fn(ret);                                         \
         }                                                               \
@@ -195,11 +173,11 @@ void translator_loop_temp_check(DisasContextBase *db);
         return fullname ## _swap(env, pc, false);                       \
     }
 
-GEN_TRANSLATOR_LD(translator_ldub, ldub, uint8_t, 0, /* no swap */ )
-GEN_TRANSLATOR_LD(translator_ldsw, ldsw, int16_t, 1, bswap16)
-GEN_TRANSLATOR_LD(translator_lduw, lduw, uint16_t, 1, bswap16)
-GEN_TRANSLATOR_LD(translator_ldl, ldl, uint32_t, 2, bswap32)
-GEN_TRANSLATOR_LD(translator_ldq, ldq, uint64_t, 3, bswap64)
+GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
+GEN_TRANSLATOR_LD(translator_ldsw, int16_t, cpu_ldsw_code, bswap16)
+GEN_TRANSLATOR_LD(translator_lduw, uint16_t, cpu_lduw_code, bswap16)
+GEN_TRANSLATOR_LD(translator_ldl, uint32_t, cpu_ldl_code, bswap32)
+GEN_TRANSLATOR_LD(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
 #undef GEN_TRANSLATOR_LD
 
 #endif  /* EXEC__TRANSLATOR_H */
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 19/41] cputlb: Rename helper_ret_ld*_cmmu to cpu_ld*_code
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (17 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 18/41] translator: Use cpu_ld*_code instead of open-coding Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 20/41] cputlb: Provide cpu_(ld,st}*_mmuidx_ra for user-only Richard Henderson
                   ` (22 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Philippe Mathieu-Daudé, Aleksandar Markovic

There are no uses of the *_cmmu names other than the bare wrapping
within the *_code inlines.  Therefore rename the functions so we
can drop the inlines.

Use abi_ptr instead of target_ulong in preparation for user-only;
the two types are identical for softmmu.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h          | 29 ++++------
 include/exec/cpu_ldst_template.h | 21 -------
 tcg/tcg.h                        | 29 ----------
 accel/tcg/cputlb.c               | 94 ++++++++------------------------
 docs/devel/loads-stores.rst      |  4 +-
 5 files changed, 36 insertions(+), 141 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 399ff6c3da..ef59ed61e4 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -450,25 +450,20 @@ void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
 #undef CPU_MMU_INDEX
 #undef MEMSUFFIX
 
-#define CPU_MMU_INDEX (cpu_mmu_index(env, true))
-#define MEMSUFFIX _code
-#define SOFTMMU_CODE_ACCESS
+uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
+uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
+uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
+uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
 
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
+static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
+{
+    return (int8_t)cpu_ldub_code(env, addr);
+}
 
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#undef SOFTMMU_CODE_ACCESS
+static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
+{
+    return (int16_t)cpu_lduw_code(env, addr);
+}
 
 #endif /* defined(CONFIG_USER_ONLY) */
 
diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
index ea39e29c19..e400979f23 100644
--- a/include/exec/cpu_ldst_template.h
+++ b/include/exec/cpu_ldst_template.h
@@ -58,25 +58,6 @@
 
 /* generic load/store macros */
 
-#ifdef SOFTMMU_CODE_ACCESS
-
-static inline RES_TYPE
-glue(glue(cpu_ld, USUFFIX), _code)(CPUArchState *env, target_ulong ptr)
-{
-    TCGMemOpIdx oi = make_memop_idx(MO_TE | SHIFT, CPU_MMU_INDEX);
-    return glue(glue(helper_ret_ld, USUFFIX), _cmmu)(env, ptr, oi, 0);
-}
-
-#if DATA_SIZE <= 2
-static inline int
-glue(glue(cpu_lds, SUFFIX), _code)(CPUArchState *env, target_ulong ptr)
-{
-    return (DATA_STYPE)glue(glue(cpu_ld, USUFFIX), _code)(env, ptr);
-}
-#endif
-
-#else
-
 static inline RES_TYPE
 glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
                                                   target_ulong ptr,
@@ -127,8 +108,6 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
     glue(glue(cpu_st, SUFFIX), _mmuidx_ra)(env, ptr, v, CPU_MMU_INDEX, 0);
 }
 
-#endif /* !SOFTMMU_CODE_ACCESS */
-
 #undef RES_TYPE
 #undef DATA_TYPE
 #undef DATA_STYPE
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 92ca10dffc..3b4f79301c 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1290,27 +1290,6 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
                        TCGMemOpIdx oi, uintptr_t retaddr);
 
-uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr);
-int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr);
-uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
-int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
-uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr);
-uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
-int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-                             TCGMemOpIdx oi, uintptr_t retaddr);
-uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr);
-
 /* Temporary aliases until backends are converted.  */
 #ifdef TARGET_WORDS_BIGENDIAN
 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
@@ -1322,10 +1301,6 @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
 # define helper_ret_stw_mmu   helper_be_stw_mmu
 # define helper_ret_stl_mmu   helper_be_stl_mmu
 # define helper_ret_stq_mmu   helper_be_stq_mmu
-# define helper_ret_lduw_cmmu  helper_be_lduw_cmmu
-# define helper_ret_ldsw_cmmu  helper_be_ldsw_cmmu
-# define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
-# define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
 #else
 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
@@ -1336,10 +1311,6 @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
 # define helper_ret_stw_mmu   helper_le_stw_mmu
 # define helper_ret_stl_mmu   helper_le_stl_mmu
 # define helper_ret_stq_mmu   helper_le_stq_mmu
-# define helper_ret_lduw_cmmu  helper_le_lduw_cmmu
-# define helper_ret_ldsw_cmmu  helper_le_ldsw_cmmu
-# define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
-# define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
 #endif
 
 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index ddd19718bf..f0e4b0aee4 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2028,98 +2028,50 @@ void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
 
 /* Code access functions.  */
 
-static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr,
+static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr,
                                TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu);
+    return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code);
 }
 
-uint8_t helper_ret_ldub_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
+uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
 {
-    return full_ldub_cmmu(env, addr, oi, retaddr);
+    TCGMemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
+    return full_ldub_code(env, addr, oi, 0);
 }
 
-int8_t helper_ret_ldsb_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
+static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr,
+                               TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return (int8_t) full_ldub_cmmu(env, addr, oi, retaddr);
+    return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_code);
 }
 
-static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                                  TCGMemOpIdx oi, uintptr_t retaddr)
+uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_LEUW, true,
-                       full_le_lduw_cmmu);
+    TCGMemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
+    return full_lduw_code(env, addr, oi, 0);
 }
 
-uint16_t helper_le_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
+static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr,
+                              TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return full_le_lduw_cmmu(env, addr, oi, retaddr);
+    return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_code);
 }
 
-int16_t helper_le_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
+uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
 {
-    return (int16_t) full_le_lduw_cmmu(env, addr, oi, retaddr);
+    TCGMemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
+    return full_ldl_code(env, addr, oi, 0);
 }
 
-static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                                  TCGMemOpIdx oi, uintptr_t retaddr)
+static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr,
+                              TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, MO_BEUW, true,
-                       full_be_lduw_cmmu);
+    return load_helper(env, addr, oi, retaddr, MO_TEQ, true, full_ldq_code);
 }
 
-uint16_t helper_be_lduw_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
+uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
 {
-    return full_be_lduw_cmmu(env, addr, oi, retaddr);
-}
-
-int16_t helper_be_ldsw_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
-{
-    return (int16_t) full_be_lduw_cmmu(env, addr, oi, retaddr);
-}
-
-static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr,
-                                  TCGMemOpIdx oi, uintptr_t retaddr)
-{
-    return load_helper(env, addr, oi, retaddr, MO_LEUL, true,
-                       full_le_ldul_cmmu);
-}
-
-uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
-{
-    return full_le_ldul_cmmu(env, addr, oi, retaddr);
-}
-
-static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulong addr,
-                                  TCGMemOpIdx oi, uintptr_t retaddr)
-{
-    return load_helper(env, addr, oi, retaddr, MO_BEUL, true,
-                       full_be_ldul_cmmu);
-}
-
-uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
-{
-    return full_be_ldul_cmmu(env, addr, oi, retaddr);
-}
-
-uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
-{
-    return load_helper(env, addr, oi, retaddr, MO_LEQ, true,
-                       helper_le_ldq_cmmu);
-}
-
-uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
-                            TCGMemOpIdx oi, uintptr_t retaddr)
-{
-    return load_helper(env, addr, oi, retaddr, MO_BEQ, true,
-                       helper_be_ldq_cmmu);
+    TCGMemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
+    return full_ldq_code(env, addr, oi, 0);
 }
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
index c74cd090e6..8a5bc912a5 100644
--- a/docs/devel/loads-stores.rst
+++ b/docs/devel/loads-stores.rst
@@ -171,8 +171,6 @@ more in line with the other memory access functions.
 
 load: ``helper_{endian}_ld{sign}{size}_mmu(env, addr, opindex, retaddr)``
 
-load (code): ``helper_{endian}_ld{sign}{size}_cmmu(env, addr, opindex, retaddr)``
-
 store: ``helper_{endian}_st{size}_mmu(env, addr, val, opindex, retaddr)``
 
 ``sign``
@@ -192,7 +190,7 @@ store: ``helper_{endian}_st{size}_mmu(env, addr, val, opindex, retaddr)``
  - ``ret`` : target endianness
 
 Regexes for git grep
- - ``\<helper_\(le\|be\|ret\)_ld[us]\?[bwlq]_c\?mmu\>``
+ - ``\<helper_\(le\|be\|ret\)_ld[us]\?[bwlq]_mmu\>``
  - ``\<helper_\(le\|be\|ret\)_st[bwlq]_mmu\>``
 
 ``address_space_*``
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 20/41] cputlb: Provide cpu_(ld,st}*_mmuidx_ra for user-only
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (18 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 19/41] cputlb: Rename helper_ret_ld*_cmmu to cpu_ld*_code Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 21/41] target/i386: Use cpu_*_mmuidx_ra instead of templates Richard Henderson
                   ` (21 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Aleksandar Markovic

This finishes the new interface began with the previous patch.
Document the interface and deprecate MMU_MODE<N>_SUFFIX.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h     |  80 +++++++++++++-
 docs/devel/loads-stores.rst | 211 ++++++++++++++++++++++++++----------
 2 files changed, 230 insertions(+), 61 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index ef59ed61e4..41b98ba801 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -25,9 +25,13 @@
  *
  * The syntax for the accessors is:
  *
- * load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
+ * load:  cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
+ *        cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
+ *        cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
  *
- * store: cpu_st{sign}{size}_{mmusuffix}(env, ptr, val)
+ * store: cpu_st{size}_{mmusuffix}(env, ptr, val)
+ *        cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
+ *        cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
  *
  * sign is:
  * (empty): for 32 and 64 bit sizes
@@ -40,9 +44,10 @@
  *   l: 32 bits
  *   q: 64 bits
  *
- * mmusuffix is one of the generic suffixes "data" or "code", or
- * (for softmmu configs)  a target-specific MMU mode suffix as defined
- * in target cpu.h.
+ * mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
+ * The "mmuidx" suffix carries an extra mmu_idx argument that specifies
+ * the index to use; the "data" and "code" suffixes take the index from
+ * cpu_mmu_index().
  */
 #ifndef CPU_LDST_H
 #define CPU_LDST_H
@@ -145,6 +150,71 @@ static inline void clear_helper_retaddr(void)
 #undef MEMSUFFIX
 #undef CODE_ACCESS
 
+/*
+ * Provide the same *_mmuidx_ra interface as for softmmu.
+ * The mmu_idx argument is ignored.
+ */
+
+static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                          int mmu_idx, uintptr_t ra)
+{
+    return cpu_ldub_data_ra(env, addr, ra);
+}
+
+static inline uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                          int mmu_idx, uintptr_t ra)
+{
+    return cpu_lduw_data_ra(env, addr, ra);
+}
+
+static inline uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                         int mmu_idx, uintptr_t ra)
+{
+    return cpu_ldl_data_ra(env, addr, ra);
+}
+
+static inline uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                         int mmu_idx, uintptr_t ra)
+{
+    return cpu_ldq_data_ra(env, addr, ra);
+}
+
+static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                     int mmu_idx, uintptr_t ra)
+{
+    return cpu_ldsb_data_ra(env, addr, ra);
+}
+
+static inline int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                     int mmu_idx, uintptr_t ra)
+{
+    return cpu_ldsw_data_ra(env, addr, ra);
+}
+
+static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                     uint32_t val, int mmu_idx, uintptr_t ra)
+{
+    cpu_stb_data_ra(env, addr, val, ra);
+}
+
+static inline void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                     uint32_t val, int mmu_idx, uintptr_t ra)
+{
+    cpu_stw_data_ra(env, addr, val, ra);
+}
+
+static inline void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                     uint32_t val, int mmu_idx, uintptr_t ra)
+{
+    cpu_stl_data_ra(env, addr, val, ra);
+}
+
+static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+                                     uint64_t val, int mmu_idx, uintptr_t ra)
+{
+    cpu_stq_data_ra(env, addr, val, ra);
+}
+
 #else
 
 /* Needed for TCG_OVERSIZED_GUEST */
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
index 8a5bc912a5..03aa9e7ff8 100644
--- a/docs/devel/loads-stores.rst
+++ b/docs/devel/loads-stores.rst
@@ -72,31 +72,34 @@ Regexes for git grep
  - ``\<ldn_\([hbl]e\)?_p\>``
  - ``\<stn_\([hbl]e\)?_p\>``
 
-``cpu_{ld,st}_*``
-~~~~~~~~~~~~~~~~~
+``cpu_{ld,st}*_mmuidx_ra``
+~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-These functions operate on a guest virtual address. Be aware
-that these functions may cause a guest CPU exception to be
-taken (e.g. for an alignment fault or MMU fault) which will
-result in guest CPU state being updated and control longjumping
-out of the function call. They should therefore only be used
-in code that is implementing emulation of the target CPU.
+These functions operate on a guest virtual address plus a context,
+known as a "mmu index" or ``mmuidx``, which controls how that virtual
+address is translated.  The meaning of the indexes are target specific,
+but specifying a particular index might be necessary if, for instance,
+the helper requires an "always as non-privileged" access rather that
+the default access for the current state of the guest CPU.
 
-These functions may throw an exception (longjmp() back out
-to the top level TCG loop). This means they must only be used
-from helper functions where the translator has saved all
-necessary CPU state before generating the helper function call.
-It's usually better to use the ``_ra`` variants described below
-from helper functions, but these functions are the right choice
-for calls made from hooks like the CPU do_interrupt hook or
-when you know for certain that the translator had to save all
-the CPU state that ``cpu_restore_state()`` would restore anyway.
+These functions may cause a guest CPU exception to be taken
+(e.g. for an alignment fault or MMU fault) which will result in
+guest CPU state being updated and control longjmp'ing out of the
+function call.  They should therefore only be used in code that is
+implementing emulation of the guest CPU.
+
+The ``retaddr`` parameter is used to control unwinding of the
+guest CPU state in case of a guest CPU exception.  This is passed
+to ``cpu_restore_state()``.  Therefore the value should either be 0,
+to indicate that the guest CPU state is already synchronized, or
+the result of ``GETPC()`` from the top level ``HELPER(foo)``
+function, which is a return address into the generated code.
 
 Function names follow the pattern:
 
-load: ``cpu_ld{sign}{size}_{mmusuffix}(env, ptr)``
+load: ``cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmuidx, retaddr)``
 
-store: ``cpu_st{size}_{mmusuffix}(env, ptr, val)``
+store: ``cpu_st{size}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
 
 ``sign``
  - (empty) : for 32 or 64 bit sizes
@@ -109,56 +112,151 @@ store: ``cpu_st{size}_{mmusuffix}(env, ptr, val)``
  - ``l`` : 32 bits
  - ``q`` : 64 bits
 
-``mmusuffix`` is one of the generic suffixes ``data`` or ``code``, or
-(for softmmu configs) a target-specific MMU mode suffix as defined
-in the target's ``cpu.h``.
+Regexes for git grep:
+ - ``\<cpu_ld[us]\?[bwlq]_mmuidx_ra\>``
+ - ``\<cpu_st[bwlq]_mmuidx_ra\>``
 
-Regexes for git grep
- - ``\<cpu_ld[us]\?[bwlq]_[a-zA-Z0-9]\+\>``
- - ``\<cpu_st[bwlq]_[a-zA-Z0-9]\+\>``
+``cpu_{ld,st}*_data_ra``
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-``cpu_{ld,st}_*_ra``
-~~~~~~~~~~~~~~~~~~~~
-
-These functions work like the ``cpu_{ld,st}_*`` functions except
-that they also take a ``retaddr`` argument. This extra argument
-allows for correct unwinding of any exception that is taken,
-and should generally be the result of GETPC() called directly
-from the top level HELPER(foo) function (i.e. the return address
-in the generated code).
+These functions work like the ``cpu_{ld,st}_mmuidx_ra`` functions
+except that the ``mmuidx`` parameter is taken from the current mode
+of the guest CPU, as determined by ``cpu_mmu_index(env, false)``.
 
 These are generally the preferred way to do accesses by guest
-virtual address from helper functions; see the documentation
-of the non-``_ra`` variants for when those would be better.
-
-Calling these functions with a ``retaddr`` argument of 0 is
-equivalent to calling the non-``_ra`` version of the function.
+virtual address from helper functions, unless the access should
+be performed with a context other than the default.
 
 Function names follow the pattern:
 
-load: ``cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)``
+load: ``cpu_ld{sign}{size}_data_ra(env, ptr, ra)``
 
-store: ``cpu_st{sign}{size}_{mmusuffix}_ra(env, ptr, val, retaddr)``
+store: ``cpu_st{size}_data_ra(env, ptr, val, ra)``
+
+``sign``
+ - (empty) : for 32 or 64 bit sizes
+ - ``u`` : unsigned
+ - ``s`` : signed
+
+``size``
+ - ``b`` : 8 bits
+ - ``w`` : 16 bits
+ - ``l`` : 32 bits
+ - ``q`` : 64 bits
+
+Regexes for git grep:
+ - ``\<cpu_ld[us]\?[bwlq]_data_ra\>``
+ - ``\<cpu_st[bwlq]_data_ra\>``
+
+``cpu_{ld,st}*_data``
+~~~~~~~~~~~~~~~~~~~~~
+
+These functions work like the ``cpu_{ld,st}_data_ra`` functions
+except that the ``retaddr`` parameter is 0, and thus does not
+unwind guest CPU state.
+
+This means they must only be used from helper functions where the
+translator has saved all necessary CPU state.  These functions are
+the right choice for calls made from hooks like the CPU ``do_interrupt``
+hook or when you know for certain that the translator had to save all
+the CPU state anyway.
+
+Function names follow the pattern:
+
+load: ``cpu_ld{sign}{size}_data(env, ptr)``
+
+store: ``cpu_st{size}_data(env, ptr, val)``
+
+``sign``
+ - (empty) : for 32 or 64 bit sizes
+ - ``u`` : unsigned
+ - ``s`` : signed
+
+``size``
+ - ``b`` : 8 bits
+ - ``w`` : 16 bits
+ - ``l`` : 32 bits
+ - ``q`` : 64 bits
 
 Regexes for git grep
- - ``\<cpu_ld[us]\?[bwlq]_[a-zA-Z0-9]\+_ra\>``
- - ``\<cpu_st[bwlq]_[a-zA-Z0-9]\+_ra\>``
+ - ``\<cpu_ld[us]\?[bwlq]_data\>``
+ - ``\<cpu_st[bwlq]_data\+\>``
 
-``helper_*_{ld,st}*mmu``
-~~~~~~~~~~~~~~~~~~~~~~~~
+``cpu_ld*_code``
+~~~~~~~~~~~~~~~~
+
+These functions perform a read for instruction execution.  The ``mmuidx``
+parameter is taken from the current mode of the guest CPU, as determined
+by ``cpu_mmu_index(env, true)``.  The ``retaddr`` parameter is 0, and
+thus does not unwind guest CPU state, because CPU state is always
+synchronized while translating instructions.  Any guest CPU exception
+that is raised will indicate an instruction execution fault rather than
+a data read fault.
+
+In general these functions should not be used directly during translation.
+There are wrapper functions that are to be used which also take care of
+plugins for tracing.
+
+Function names follow the pattern:
+
+load: ``cpu_ld{sign}{size}_code(env, ptr)``
+
+``sign``
+ - (empty) : for 32 or 64 bit sizes
+ - ``u`` : unsigned
+ - ``s`` : signed
+
+``size``
+ - ``b`` : 8 bits
+ - ``w`` : 16 bits
+ - ``l`` : 32 bits
+ - ``q`` : 64 bits
+
+Regexes for git grep:
+ - ``\<cpu_ld[us]\?[bwlq]_code\>``
+
+``translator_ld*``
+~~~~~~~~~~~~~~~~~~
+
+These functions are a wrapper for ``cpu_ld*_code`` which also perform
+any actions required by any tracing plugins.  They are only to be
+called during the translator callback ``translate_insn``.
+
+There is a set of functions ending in ``_swap`` which, if the parameter
+is true, returns the value in the endianness that is the reverse of
+the guest native endianness, as determined by ``TARGET_WORDS_BIGENDIAN``.
+
+Function names follow the pattern:
+
+load: ``translator_ld{sign}{size}(env, ptr)``
+
+swap: ``translator_ld{sign}{size}_swap(env, ptr, swap)``
+
+``sign``
+ - (empty) : for 32 or 64 bit sizes
+ - ``u`` : unsigned
+ - ``s`` : signed
+
+``size``
+ - ``b`` : 8 bits
+ - ``w`` : 16 bits
+ - ``l`` : 32 bits
+ - ``q`` : 64 bits
+
+Regexes for git grep
+ - ``\<translator_ld[us]\?[bwlq]\(_swap\)\?\>``
+
+``helper_*_{ld,st}*_mmu``
+~~~~~~~~~~~~~~~~~~~~~~~~~
 
 These functions are intended primarily to be called by the code
 generated by the TCG backend. They may also be called by target
-CPU helper function code. Like the ``cpu_{ld,st}_*_ra`` functions
-they perform accesses by guest virtual address; the difference is
-that these functions allow you to specify an ``opindex`` parameter
-which encodes (among other things) the mmu index to use for the
-access. This is necessary if your helper needs to make an access
-via a specific mmu index (for instance, an "always as non-privileged"
-access) rather than using the default mmu index for the current state
-of the guest CPU.
+CPU helper function code. Like the ``cpu_{ld,st}_mmuidx_ra`` functions
+they perform accesses by guest virtual address, with a given ``mmuidx``.
 
-The ``opindex`` parameter should be created by calling ``make_memop_idx()``.
+These functions specify an ``opindex`` parameter which encodes
+(among other things) the mmu index to use for the access.  This parameter
+should be created by calling ``make_memop_idx()``.
 
 The ``retaddr`` parameter should be the result of GETPC() called directly
 from the top level HELPER(foo) function (or 0 if no guest CPU state
@@ -166,8 +264,9 @@ unwinding is required).
 
 **TODO** The names of these functions are a bit odd for historical
 reasons because they were originally expected to be called only from
-within generated code. We should rename them to bring them
-more in line with the other memory access functions.
+within generated code. We should rename them to bring them more in
+line with the other memory access functions. The explicit endianness
+is the only feature they have beyond ``*_mmuidx_ra``.
 
 load: ``helper_{endian}_ld{sign}{size}_mmu(env, addr, opindex, retaddr)``
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 21/41] target/i386: Use cpu_*_mmuidx_ra instead of templates
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (19 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 20/41] cputlb: Provide cpu_(ld,st}*_mmuidx_ra for user-only Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 22/41] cputlb: Expand cpu_ldst_useronly_template.h in user-exec.c Richard Henderson
                   ` (20 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Eduardo Habkost, Paolo Bonzini

Do not use exec/cpu_ldst_{,useronly_}template.h directly,
but instead use the functional interface.

Cc: Eduardo Habkost <ehabkost@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/seg_helper.c | 56 ++++++++++++++++++++--------------------
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c
index 87a627f9dc..b96de068ca 100644
--- a/target/i386/seg_helper.c
+++ b/target/i386/seg_helper.c
@@ -37,37 +37,37 @@
 # define LOG_PCALL_STATE(cpu) do { } while (0)
 #endif
 
-#ifdef CONFIG_USER_ONLY
-#define MEMSUFFIX _kernel
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_useronly_template.h"
+/*
+ * TODO: Convert callers to compute cpu_mmu_index_kernel once
+ * and use *_mmuidx_ra directly.
+ */
+#define cpu_ldub_kernel_ra(e, p, r) \
+    cpu_ldub_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
+#define cpu_lduw_kernel_ra(e, p, r) \
+    cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
+#define cpu_ldl_kernel_ra(e, p, r) \
+    cpu_ldl_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
+#define cpu_ldq_kernel_ra(e, p, r) \
+    cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
 
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_useronly_template.h"
+#define cpu_stb_kernel_ra(e, p, v, r) \
+    cpu_stb_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
+#define cpu_stw_kernel_ra(e, p, v, r) \
+    cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
+#define cpu_stl_kernel_ra(e, p, v, r) \
+    cpu_stl_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
+#define cpu_stq_kernel_ra(e, p, v, r) \
+    cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
 
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_useronly_template.h"
+#define cpu_ldub_kernel(e, p)    cpu_ldub_kernel_ra(e, p, 0)
+#define cpu_lduw_kernel(e, p)    cpu_lduw_kernel_ra(e, p, 0)
+#define cpu_ldl_kernel(e, p)     cpu_ldl_kernel_ra(e, p, 0)
+#define cpu_ldq_kernel(e, p)     cpu_ldq_kernel_ra(e, p, 0)
 
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_useronly_template.h"
-#undef MEMSUFFIX
-#else
-#define CPU_MMU_INDEX (cpu_mmu_index_kernel(env))
-#define MEMSUFFIX _kernel
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif
+#define cpu_stb_kernel(e, p, v)  cpu_stb_kernel_ra(e, p, v, 0)
+#define cpu_stw_kernel(e, p, v)  cpu_stw_kernel_ra(e, p, v, 0)
+#define cpu_stl_kernel(e, p, v)  cpu_stl_kernel_ra(e, p, v, 0)
+#define cpu_stq_kernel(e, p, v)  cpu_stq_kernel_ra(e, p, v, 0)
 
 /* return non zero if error */
 static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr,
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 22/41] cputlb: Expand cpu_ldst_useronly_template.h in user-exec.c
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (20 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 21/41] target/i386: Use cpu_*_mmuidx_ra instead of templates Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 23/41] target/nios2: Remove MMU_MODE{0,1}_SUFFIX Richard Henderson
                   ` (19 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

With the tracing hooks, the inline functions are no longer
so simple.  Reduce the amount of preprocessor obfuscation
by expanding the text of each of the functions generated.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h                   |  54 +++--
 include/exec/cpu_ldst_useronly_template.h | 159 ---------------
 accel/tcg/user-exec.c                     | 236 ++++++++++++++++++++++
 3 files changed, 262 insertions(+), 187 deletions(-)
 delete mode 100644 include/exec/cpu_ldst_useronly_template.h

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 41b98ba801..0f3c49a005 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -120,35 +120,33 @@ static inline void clear_helper_retaddr(void)
 
 /* In user-only mode we provide only the _code and _data accessors. */
 
-#define MEMSUFFIX _data
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_useronly_template.h"
+uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
+uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
+uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
+uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
+int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
+int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
 
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_useronly_template.h"
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
+uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
+uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
+uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
+int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
 
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_useronly_template.h"
+void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
+void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
 
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_useronly_template.h"
-#undef MEMSUFFIX
-
-#define MEMSUFFIX _code
-#define CODE_ACCESS
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_useronly_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_useronly_template.h"
-#undef MEMSUFFIX
-#undef CODE_ACCESS
+void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint32_t val, uintptr_t retaddr);
+void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint32_t val, uintptr_t retaddr);
+void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint32_t val, uintptr_t retaddr);
+void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint64_t val, uintptr_t retaddr);
 
 /*
  * Provide the same *_mmuidx_ra interface as for softmmu.
@@ -520,6 +518,8 @@ void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
 #undef CPU_MMU_INDEX
 #undef MEMSUFFIX
 
+#endif /* defined(CONFIG_USER_ONLY) */
+
 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
@@ -535,8 +535,6 @@ static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
     return (int16_t)cpu_lduw_code(env, addr);
 }
 
-#endif /* defined(CONFIG_USER_ONLY) */
-
 /**
  * tlb_vaddr_to_host:
  * @env: CPUArchState
diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h
deleted file mode 100644
index e5a3d1983a..0000000000
--- a/include/exec/cpu_ldst_useronly_template.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- *  User-only accessor function support
- *
- * Generate inline load/store functions for one data size.
- *
- * Generate a store function as well as signed and unsigned loads.
- *
- * Not used directly but included from cpu_ldst.h.
- *
- *  Copyright (c) 2015 Linaro Limited
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#if !defined(CODE_ACCESS)
-#include "trace-root.h"
-#endif
-
-#include "trace/mem.h"
-
-#if DATA_SIZE == 8
-#define SUFFIX q
-#define USUFFIX q
-#define DATA_TYPE uint64_t
-#define SHIFT 3
-#elif DATA_SIZE == 4
-#define SUFFIX l
-#define USUFFIX l
-#define DATA_TYPE uint32_t
-#define SHIFT 2
-#elif DATA_SIZE == 2
-#define SUFFIX w
-#define USUFFIX uw
-#define DATA_TYPE uint16_t
-#define DATA_STYPE int16_t
-#define SHIFT 1
-#elif DATA_SIZE == 1
-#define SUFFIX b
-#define USUFFIX ub
-#define DATA_TYPE uint8_t
-#define DATA_STYPE int8_t
-#define SHIFT 0
-#else
-#error unsupported data size
-#endif
-
-#if DATA_SIZE == 8
-#define RES_TYPE uint64_t
-#else
-#define RES_TYPE uint32_t
-#endif
-
-static inline RES_TYPE
-glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
-{
-    RES_TYPE ret;
-#ifdef CODE_ACCESS
-    set_helper_retaddr(1);
-    ret = glue(glue(ld, USUFFIX), _p)(g2h(ptr));
-    clear_helper_retaddr();
-#else
-    MemOp op = MO_TE | SHIFT;
-    uint16_t meminfo = trace_mem_get_info(op, MMU_USER_IDX, false);
-    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
-    ret = glue(glue(ld, USUFFIX), _p)(g2h(ptr));
-#endif
-    return ret;
-}
-
-#ifndef CODE_ACCESS
-static inline RES_TYPE
-glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
-                                                  abi_ptr ptr,
-                                                  uintptr_t retaddr)
-{
-    RES_TYPE ret;
-    set_helper_retaddr(retaddr);
-    ret = glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(env, ptr);
-    clear_helper_retaddr();
-    return ret;
-}
-#endif
-
-#if DATA_SIZE <= 2
-static inline int
-glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr)
-{
-    int ret;
-#ifdef CODE_ACCESS
-    set_helper_retaddr(1);
-    ret = glue(glue(lds, SUFFIX), _p)(g2h(ptr));
-    clear_helper_retaddr();
-#else
-    MemOp op = MO_TE | MO_SIGN | SHIFT;
-    uint16_t meminfo = trace_mem_get_info(op, MMU_USER_IDX, false);
-    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
-    ret = glue(glue(lds, SUFFIX), _p)(g2h(ptr));
-    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
-#endif
-    return ret;
-}
-
-#ifndef CODE_ACCESS
-static inline int
-glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
-                                                  abi_ptr ptr,
-                                                  uintptr_t retaddr)
-{
-    int ret;
-    set_helper_retaddr(retaddr);
-    ret = glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(env, ptr);
-    clear_helper_retaddr();
-    return ret;
-}
-#endif /* CODE_ACCESS */
-#endif /* DATA_SIZE <= 2 */
-
-#ifndef CODE_ACCESS
-static inline void
-glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr,
-                                      RES_TYPE v)
-{
-    MemOp op = MO_TE | SHIFT;
-    uint16_t meminfo = trace_mem_get_info(op, MMU_USER_IDX, true);
-    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
-    glue(glue(st, SUFFIX), _p)(g2h(ptr), v);
-    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
-}
-
-static inline void
-glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
-                                                  abi_ptr ptr,
-                                                  RES_TYPE v,
-                                                  uintptr_t retaddr)
-{
-    set_helper_retaddr(retaddr);
-    glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(env, ptr, v);
-    clear_helper_retaddr();
-}
-#endif
-
-#undef RES_TYPE
-#undef DATA_TYPE
-#undef DATA_STYPE
-#undef SUFFIX
-#undef USUFFIX
-#undef DATA_SIZE
-#undef SHIFT
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index b09f7a1577..79da4219bb 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -26,6 +26,8 @@
 #include "translate-all.h"
 #include "exec/helper-proto.h"
 #include "qemu/atomic128.h"
+#include "trace-root.h"
+#include "trace/mem.h"
 
 #undef EAX
 #undef ECX
@@ -734,6 +736,240 @@ int cpu_signal_handler(int host_signum, void *pinfo,
 
 /* The softmmu versions of these helpers are in cputlb.c.  */
 
+uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
+{
+    uint32_t ret;
+    uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    ret = ldub_p(g2h(ptr));
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+    return ret;
+}
+
+int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
+{
+    int ret;
+    uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    ret = ldsb_p(g2h(ptr));
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+    return ret;
+}
+
+uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr)
+{
+    uint32_t ret;
+    uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    ret = lduw_p(g2h(ptr));
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+    return ret;
+}
+
+int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr)
+{
+    int ret;
+    uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    ret = ldsw_p(g2h(ptr));
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+    return ret;
+}
+
+uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr)
+{
+    uint32_t ret;
+    uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    ret = ldl_p(g2h(ptr));
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+    return ret;
+}
+
+uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr)
+{
+    uint64_t ret;
+    uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    ret = ldq_p(g2h(ptr));
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+    return ret;
+}
+
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+{
+    uint32_t ret;
+
+    set_helper_retaddr(retaddr);
+    ret = cpu_ldub_data(env, ptr);
+    clear_helper_retaddr();
+    return ret;
+}
+
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+{
+    int ret;
+
+    set_helper_retaddr(retaddr);
+    ret = cpu_ldsb_data(env, ptr);
+    clear_helper_retaddr();
+    return ret;
+}
+
+uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+{
+    uint32_t ret;
+
+    set_helper_retaddr(retaddr);
+    ret = cpu_lduw_data(env, ptr);
+    clear_helper_retaddr();
+    return ret;
+}
+
+int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+{
+    int ret;
+
+    set_helper_retaddr(retaddr);
+    ret = cpu_ldsw_data(env, ptr);
+    clear_helper_retaddr();
+    return ret;
+}
+
+uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+{
+    uint32_t ret;
+
+    set_helper_retaddr(retaddr);
+    ret = cpu_ldl_data(env, ptr);
+    clear_helper_retaddr();
+    return ret;
+}
+
+uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+{
+    uint64_t ret;
+
+    set_helper_retaddr(retaddr);
+    ret = cpu_ldq_data(env, ptr);
+    clear_helper_retaddr();
+    return ret;
+}
+
+void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
+{
+    uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    stb_p(g2h(ptr), val);
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+}
+
+void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
+{
+    uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    stw_p(g2h(ptr), val);
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+}
+
+void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
+{
+    uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    stl_p(g2h(ptr), val);
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+}
+
+void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
+{
+    uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true);
+
+    trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+    stq_p(g2h(ptr), val);
+    qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+}
+
+void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint32_t val, uintptr_t retaddr)
+{
+    set_helper_retaddr(retaddr);
+    cpu_stb_data(env, ptr, val);
+    clear_helper_retaddr();
+}
+
+void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint32_t val, uintptr_t retaddr)
+{
+    set_helper_retaddr(retaddr);
+    cpu_stw_data(env, ptr, val);
+    clear_helper_retaddr();
+}
+
+void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint32_t val, uintptr_t retaddr)
+{
+    set_helper_retaddr(retaddr);
+    cpu_stl_data(env, ptr, val);
+    clear_helper_retaddr();
+}
+
+void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
+                     uint64_t val, uintptr_t retaddr)
+{
+    set_helper_retaddr(retaddr);
+    cpu_stq_data(env, ptr, val);
+    clear_helper_retaddr();
+}
+
+uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr)
+{
+    uint32_t ret;
+
+    set_helper_retaddr(1);
+    ret = ldub_p(g2h(ptr));
+    clear_helper_retaddr();
+    return ret;
+}
+
+uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr)
+{
+    uint32_t ret;
+
+    set_helper_retaddr(1);
+    ret = lduw_p(g2h(ptr));
+    clear_helper_retaddr();
+    return ret;
+}
+
+uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr)
+{
+    uint32_t ret;
+
+    set_helper_retaddr(1);
+    ret = ldl_p(g2h(ptr));
+    clear_helper_retaddr();
+    return ret;
+}
+
+uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr)
+{
+    uint64_t ret;
+
+    set_helper_retaddr(1);
+    ret = ldq_p(g2h(ptr));
+    clear_helper_retaddr();
+    return ret;
+}
+
 /* Do not allow unaligned operations to proceed.  Return the host address.  */
 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
                                int size, uintptr_t retaddr)
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 23/41] target/nios2: Remove MMU_MODE{0,1}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (21 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 22/41] cputlb: Expand cpu_ldst_useronly_template.h in user-exec.c Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 24/41] target/alpha: " Richard Henderson
                   ` (18 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Marek Vasut, peter.maydell, Chris Wulff,
	Philippe Mathieu-Daudé,
	Alex Bennée

The functions generated by these macros are unused.

Cc: Chris Wulff <crwulff@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/nios2/cpu.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 361b06ffeb..78f633f970 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -217,8 +217,6 @@ void do_nios2_semihosting(CPUNios2State *env);
 #define CPU_SAVE_VERSION 1
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _user
 #define MMU_SUPERVISOR_IDX  0
 #define MMU_USER_IDX        1
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 24/41] target/alpha: Remove MMU_MODE{0,1}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (22 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 23/41] target/nios2: Remove MMU_MODE{0,1}_SUFFIX Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 25/41] target/cris: " Richard Henderson
                   ` (17 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

The functions generated by these macros are unused.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/cpu.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index a530249a5b..3f782c0efe 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -193,8 +193,6 @@ enum {
    PALcode cheats and usees the KSEG mapping for its code+data rather than
    physical addresses.  */
 
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _user
 #define MMU_KERNEL_IDX   0
 #define MMU_USER_IDX     1
 #define MMU_PHYS_IDX     2
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 25/41] target/cris: Remove MMU_MODE{0,1}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (23 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 24/41] target/alpha: " Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 26/41] target/i386: Remove MMU_MODE{0,1,2}_SUFFIX Richard Henderson
                   ` (16 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Edgar E . Iglesias

The functions generated by these macros are unused.

Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/cris/cpu.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index aba0a66474..bc43bc23a1 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -252,8 +252,6 @@ enum {
 #define cpu_signal_handler cpu_cris_signal_handler
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _user
 #define MMU_USER_IDX 1
 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
 {
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 26/41] target/i386: Remove MMU_MODE{0,1,2}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (24 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 25/41] target/cris: " Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 27/41] target/microblaze: " Richard Henderson
                   ` (15 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Eduardo Habkost, Paolo Bonzini

The functions generated by these macros are unused.

Cc: Eduardo Habkost <ehabkost@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/cpu.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index af282936a7..1b4b90556c 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1952,9 +1952,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
 #define cpu_list x86_cpu_list
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _ksmap
-#define MMU_MODE1_SUFFIX _user
-#define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
 #define MMU_KSMAP_IDX   0
 #define MMU_USER_IDX    1
 #define MMU_KNOSMAP_IDX 2
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 27/41] target/microblaze: Remove MMU_MODE{0,1,2}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (25 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 26/41] target/i386: Remove MMU_MODE{0,1,2}_SUFFIX Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 28/41] target/sh4: Remove MMU_MODE{0,1}_SUFFIX Richard Henderson
                   ` (14 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Edgar E . Iglesias

The functions generated by these macros are unused.

Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/cpu.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 95773089aa..32522f606b 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -328,9 +328,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
 #define cpu_signal_handler cpu_mb_signal_handler
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _nommu
-#define MMU_MODE1_SUFFIX _kernel
-#define MMU_MODE2_SUFFIX _user
 #define MMU_NOMMU_IDX   0
 #define MMU_KERNEL_IDX  1
 #define MMU_USER_IDX    2
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 28/41] target/sh4: Remove MMU_MODE{0,1}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (26 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 27/41] target/microblaze: " Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 29/41] target/unicore32: " Richard Henderson
                   ` (13 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Aurelien Jarno

The functions generated by these macros are unused.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/cpu.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index ecaa7a18a9..452a596e67 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -254,8 +254,6 @@ void cpu_load_tlb(CPUSH4State * env);
 #define cpu_list sh4_cpu_list
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _user
 #define MMU_USER_IDX 1
 static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
 {
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 29/41] target/unicore32: Remove MMU_MODE{0,1}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (27 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 28/41] target/sh4: Remove MMU_MODE{0,1}_SUFFIX Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 30/41] target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX Richard Henderson
                   ` (12 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Guan Xuetao,
	Philippe Mathieu-Daudé

The functions generated by these macros are unused.

Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/unicore32/cpu.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 50ed9dd99c..7a32e086ed 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -133,8 +133,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
 int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _user
 #define MMU_USER_IDX 1
 static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
 {
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 30/41] target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (28 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 29/41] target/unicore32: " Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 31/41] target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0, 1}_SUFFIX Richard Henderson
                   ` (11 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Max Filippov

The functions generated by these macros are unused.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/xtensa/cpu.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 75e65df597..493f4fc80c 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -689,10 +689,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
 }
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _ring0
-#define MMU_MODE1_SUFFIX _ring1
-#define MMU_MODE2_SUFFIX _ring2
-#define MMU_MODE3_SUFFIX _ring3
 #define MMU_USER_IDX 3
 
 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 31/41] target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0, 1}_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (29 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 30/41] target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX Richard Henderson
                   ` (10 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Laurent Vivier

The generated *_user functions are unused.  The *_kernel functions
have a couple of users in op_helper.c; use *_mmuidx_ra instead,
with MMU_KERNEL_IDX.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Use *_mmuidx_ra directly, without intermediate macros.
---
 target/m68k/cpu.h       |  2 --
 target/m68k/op_helper.c | 77 +++++++++++++++++++++++++----------------
 2 files changed, 47 insertions(+), 32 deletions(-)

diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 11c71fa962..3de8e06dfe 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -519,8 +519,6 @@ enum {
 #define cpu_list m68k_cpu_list
 
 /* MMU modes definitions */
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _user
 #define MMU_KERNEL_IDX 0
 #define MMU_USER_IDX 1
 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index bc4f845e3f..202498deb5 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -42,8 +42,8 @@ static void cf_rte(CPUM68KState *env)
     uint32_t fmt;
 
     sp = env->aregs[7];
-    fmt = cpu_ldl_kernel(env, sp);
-    env->pc = cpu_ldl_kernel(env, sp + 4);
+    fmt = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
+    env->pc = cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0);
     sp |= (fmt >> 28) & 3;
     env->aregs[7] = sp + 8;
 
@@ -58,13 +58,13 @@ static void m68k_rte(CPUM68KState *env)
 
     sp = env->aregs[7];
 throwaway:
-    sr = cpu_lduw_kernel(env, sp);
+    sr = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
     sp += 2;
-    env->pc = cpu_ldl_kernel(env, sp);
+    env->pc = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
     sp += 4;
     if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) {
         /*  all except 68000 */
-        fmt = cpu_lduw_kernel(env, sp);
+        fmt = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
         sp += 2;
         switch (fmt >> 12) {
         case 0:
@@ -260,12 +260,12 @@ static void cf_interrupt_all(CPUM68KState *env, int is_hw)
     /* ??? This could cause MMU faults.  */
     sp &= ~3;
     sp -= 4;
-    cpu_stl_kernel(env, sp, retaddr);
+    cpu_stl_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0);
     sp -= 4;
-    cpu_stl_kernel(env, sp, fmt);
+    cpu_stl_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0);
     env->aregs[7] = sp;
     /* Jump to vector.  */
-    env->pc = cpu_ldl_kernel(env, env->vbr + vector);
+    env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
 }
 
 static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
@@ -278,23 +278,24 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
         switch (format) {
         case 4:
             *sp -= 4;
-            cpu_stl_kernel(env, *sp, env->pc);
+            cpu_stl_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0);
             *sp -= 4;
-            cpu_stl_kernel(env, *sp, addr);
+            cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
             break;
         case 3:
         case 2:
             *sp -= 4;
-            cpu_stl_kernel(env, *sp, addr);
+            cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
             break;
         }
         *sp -= 2;
-        cpu_stw_kernel(env, *sp, (format << 12) + (cs->exception_index << 2));
+        cpu_stw_mmuidx_ra(env, *sp, (format << 12) + (cs->exception_index << 2),
+                          MMU_KERNEL_IDX, 0);
     }
     *sp -= 4;
-    cpu_stl_kernel(env, *sp, retaddr);
+    cpu_stl_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0);
     *sp -= 2;
-    cpu_stw_kernel(env, *sp, sr);
+    cpu_stw_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0);
 }
 
 static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
@@ -353,36 +354,52 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
             cpu_abort(cs, "DOUBLE MMU FAULT\n");
         }
         env->mmu.fault = true;
+        /* push data 3 */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* push data 3 */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* push data 2 */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* push data 2 */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* push data 1 */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* push data 1 */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 1 / push data 0 */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* write back 1 / push data 0 */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 1 address */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* write back 1 address */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 2 data */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* write back 2 data */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 2 address */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* write back 2 address */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 3 data */
         sp -= 4;
-        cpu_stl_kernel(env, sp, 0); /* write back 3 data */
+        cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 3 address */
         sp -= 4;
-        cpu_stl_kernel(env, sp, env->mmu.ar); /* write back 3 address */
+        cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+        /* fault address */
         sp -= 4;
-        cpu_stl_kernel(env, sp, env->mmu.ar); /* fault address */
+        cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+        /* write back 1 status */
         sp -= 2;
-        cpu_stw_kernel(env, sp, 0); /* write back 1 status */
+        cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 2 status */
         sp -= 2;
-        cpu_stw_kernel(env, sp, 0); /* write back 2 status */
+        cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* write back 3 status */
         sp -= 2;
-        cpu_stw_kernel(env, sp, 0); /* write back 3 status */
+        cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+        /* special status word */
         sp -= 2;
-        cpu_stw_kernel(env, sp, env->mmu.ssw); /* special status word */
+        cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
+        /* effective address */
         sp -= 4;
-        cpu_stl_kernel(env, sp, env->mmu.ar); /* effective address */
+        cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+
         do_stack_frame(env, &sp, 7, oldsr, 0, retaddr);
         env->mmu.fault = false;
         if (qemu_loglevel_mask(CPU_LOG_INT)) {
@@ -414,7 +431,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
 
     env->aregs[7] = sp;
     /* Jump to vector.  */
-    env->pc = cpu_ldl_kernel(env, env->vbr + vector);
+    env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
 }
 
 static void do_interrupt_all(CPUM68KState *env, int is_hw)
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (30 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 31/41] target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0, 1}_SUFFIX Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-02-01 20:12   ` Philippe Mathieu-Daudé
  2020-01-08  3:45 ` [PULL 33/41] target/s390x: " Richard Henderson
                   ` (9 subsequent siblings)
  41 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Philippe Mathieu-Daudé,
	Aleksandar Markovic, Aleksandar Rikalo, Alex Bennée,
	Aurelien Jarno

The separate suffixed functions were used to construct
some do_##insn function switched on mmu_idx.  The interface
is exactly identical to the *_mmuidx_ra functions.  Replace
them directly and remove the constructions.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/cpu.h       |   4 -
 target/mips/op_helper.c | 182 +++++++++++++---------------------------
 2 files changed, 60 insertions(+), 126 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index ca00f41daf..c218ccc4a8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1147,10 +1147,6 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
  * MMU modes definitions. We carefully match the indices with our
  * hflags layout.
  */
-#define MMU_MODE0_SUFFIX _kernel
-#define MMU_MODE1_SUFFIX _super
-#define MMU_MODE2_SUFFIX _user
-#define MMU_MODE3_SUFFIX _error
 #define MMU_USER_IDX 2
 
 static inline int hflags_mmu_index(uint32_t hflags)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 18fcee4a78..79d44da6fa 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -52,69 +52,6 @@ static void raise_exception(CPUMIPSState *env, uint32_t exception)
     do_raise_exception(env, exception, 0);
 }
 
-#if defined(CONFIG_USER_ONLY)
-#define HELPER_LD(name, insn, type)                                     \
-static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
-                             int mem_idx, uintptr_t retaddr)            \
-{                                                                       \
-    return (type) cpu_##insn##_data_ra(env, addr, retaddr);             \
-}
-#else
-#define HELPER_LD(name, insn, type)                                     \
-static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
-                             int mem_idx, uintptr_t retaddr)            \
-{                                                                       \
-    switch (mem_idx) {                                                  \
-    case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr);   \
-    case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr);    \
-    default:                                                            \
-    case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr);     \
-    case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr);    \
-    }                                                                   \
-}
-#endif
-HELPER_LD(lw, ldl, int32_t)
-#if defined(TARGET_MIPS64)
-HELPER_LD(ld, ldq, int64_t)
-#endif
-#undef HELPER_LD
-
-#if defined(CONFIG_USER_ONLY)
-#define HELPER_ST(name, insn, type)                                     \
-static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
-                             type val, int mem_idx, uintptr_t retaddr)  \
-{                                                                       \
-    cpu_##insn##_data_ra(env, addr, val, retaddr);                      \
-}
-#else
-#define HELPER_ST(name, insn, type)                                     \
-static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
-                             type val, int mem_idx, uintptr_t retaddr)  \
-{                                                                       \
-    switch (mem_idx) {                                                  \
-    case 0:                                                             \
-        cpu_##insn##_kernel_ra(env, addr, val, retaddr);                \
-        break;                                                          \
-    case 1:                                                             \
-        cpu_##insn##_super_ra(env, addr, val, retaddr);                 \
-        break;                                                          \
-    default:                                                            \
-    case 2:                                                             \
-        cpu_##insn##_user_ra(env, addr, val, retaddr);                  \
-        break;                                                          \
-    case 3:                                                             \
-        cpu_##insn##_error_ra(env, addr, val, retaddr);                 \
-        break;                                                          \
-    }                                                                   \
-}
-#endif
-HELPER_ST(sb, stb, uint8_t)
-HELPER_ST(sw, stl, uint32_t)
-#if defined(TARGET_MIPS64)
-HELPER_ST(sd, stq, uint64_t)
-#endif
-#undef HELPER_ST
-
 /* 64 bits arithmetic for 32 bits hosts */
 static inline uint64_t get_HILO(CPUMIPSState *env)
 {
@@ -379,12 +316,12 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
     }                                                                         \
     env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC());             \
     env->lladdr = arg;                                                        \
-    env->llval = do_##insn(env, arg, mem_idx, GETPC());                       \
+    env->llval = cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC());          \
     return env->llval;                                                        \
 }
-HELPER_LD_ATOMIC(ll, lw, 0x3)
+HELPER_LD_ATOMIC(ll, ldl, 0x3)
 #ifdef TARGET_MIPS64
-HELPER_LD_ATOMIC(lld, ld, 0x7)
+HELPER_LD_ATOMIC(lld, ldq, 0x7)
 #endif
 #undef HELPER_LD_ATOMIC
 #endif
@@ -400,42 +337,42 @@ HELPER_LD_ATOMIC(lld, ld, 0x7)
 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
                 int mem_idx)
 {
-    do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
+    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
 
     if (GET_LMASK(arg2) <= 2) {
-        do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK(arg2) <= 1) {
-        do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK(arg2) == 0) {
-        do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
+                          mem_idx, GETPC());
     }
 }
 
 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
                 int mem_idx)
 {
-    do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
+    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 
     if (GET_LMASK(arg2) >= 1) {
-        do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK(arg2) >= 2) {
-        do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK(arg2) == 3) {
-        do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
+                          mem_idx, GETPC());
     }
 }
 
@@ -453,82 +390,82 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
                 int mem_idx)
 {
-    do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
+    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
 
     if (GET_LMASK64(arg2) <= 6) {
-        do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) <= 5) {
-        do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) <= 4) {
-        do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) <= 3) {
-        do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) <= 2) {
-        do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) <= 1) {
-        do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) <= 0) {
-        do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
+                          mem_idx, GETPC());
     }
 }
 
 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
                 int mem_idx)
 {
-    do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
+    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
 
     if (GET_LMASK64(arg2) >= 1) {
-        do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) >= 2) {
-        do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) >= 3) {
-        do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) >= 4) {
-        do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) >= 5) {
-        do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) >= 6) {
-        do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
+                          mem_idx, GETPC());
     }
 
     if (GET_LMASK64(arg2) == 7) {
-        do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
-              GETPC());
+        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
+                          mem_idx, GETPC());
     }
 }
 #endif /* TARGET_MIPS64 */
@@ -546,14 +483,14 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 
         for (i = 0; i < base_reglist; i++) {
             env->active_tc.gpr[multiple_regs[i]] =
-                (target_long)do_lw(env, addr, mem_idx, GETPC());
+                (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
             addr += 4;
         }
     }
 
     if (do_r31) {
-        env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
-                                                    GETPC());
+        env->active_tc.gpr[31] =
+            (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
     }
 }
 
@@ -567,14 +504,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
         target_ulong i;
 
         for (i = 0; i < base_reglist; i++) {
-            do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
-                  GETPC());
+            cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
+                              mem_idx, GETPC());
             addr += 4;
         }
     }
 
     if (do_r31) {
-        do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
+        cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
     }
 }
 
@@ -589,14 +526,15 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
         target_ulong i;
 
         for (i = 0; i < base_reglist; i++) {
-            env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
-                                                         GETPC());
+            env->active_tc.gpr[multiple_regs[i]] =
+                cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
             addr += 8;
         }
     }
 
     if (do_r31) {
-        env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
+        env->active_tc.gpr[31] =
+            cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
     }
 }
 
@@ -610,14 +548,14 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
         target_ulong i;
 
         for (i = 0; i < base_reglist; i++) {
-            do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
-                  GETPC());
+            cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
+                              mem_idx, GETPC());
             addr += 8;
         }
     }
 
     if (do_r31) {
-        do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
+        cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
     }
 }
 #endif
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 33/41] target/s390x: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (31 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 34/41] target/ppc: " Richard Henderson
                   ` (8 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	David Hildenbrand

The generated functions aside from *_real are unused.
The *_real functions have a couple of users in mem_helper.c;
use *_mmuidx_ra instead, with MMU_REAL_IDX.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Use *_mmuidx_ra directly, without intermediate macros.
---
 target/s390x/cpu.h        |  5 -----
 target/s390x/mem_helper.c | 10 +++++-----
 2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index e195e5c7c8..8a557fd8d1 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -36,11 +36,6 @@
 
 #define TARGET_INSN_START_EXTRA_WORDS 2
 
-#define MMU_MODE0_SUFFIX _primary
-#define MMU_MODE1_SUFFIX _secondary
-#define MMU_MODE2_SUFFIX _home
-#define MMU_MODE3_SUFFIX _real
-
 #define MMU_USER_IDX 0
 
 #define S390_MAX_CPUS 248
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 20a84b3912..428bde4c54 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -2026,7 +2026,7 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64_t real_addr)
     real_addr = wrap_address(env, real_addr) & TARGET_PAGE_MASK;
 
     for (i = 0; i < TARGET_PAGE_SIZE; i += 8) {
-        cpu_stq_real_ra(env, real_addr + i, 0, ra);
+        cpu_stq_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra);
     }
 
     return 0;
@@ -2260,11 +2260,11 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
         for (i = 0; i < entries; i++) {
             /* addresses are not wrapped in 24/31bit mode but table index is */
             raddr = table + ((index + i) & 0x7ff) * sizeof(entry);
-            entry = cpu_ldq_real_ra(env, raddr, ra);
+            entry = cpu_ldq_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra);
             if (!(entry & REGION_ENTRY_I)) {
                 /* we are allowed to not store if already invalid */
                 entry |= REGION_ENTRY_I;
-                cpu_stq_real_ra(env, raddr, entry, ra);
+                cpu_stq_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra);
             }
         }
     }
@@ -2291,9 +2291,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
     pte_addr += VADDR_PAGE_TX(vaddr) * 8;
 
     /* Mark the page table entry as invalid */
-    pte = cpu_ldq_real_ra(env, pte_addr, ra);
+    pte = cpu_ldq_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra);
     pte |= PAGE_ENTRY_I;
-    cpu_stq_real_ra(env, pte_addr, pte, ra);
+    cpu_stq_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra);
 
     /* XXX we exploit the fact that Linux passes the exact virtual
        address here - it's not obliged to! */
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 34/41] target/ppc: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (32 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 33/41] target/s390x: " Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 35/41] cputlb: Remove support for MMU_MODE*_SUFFIX Richard Henderson
                   ` (7 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	David Gibson

There are only two uses.  Within dcbz_common, the local variable
mmu_idx already contains the epid computation, and we can avoid
repeating it for the store.  Within helper_icbiep, the usage is
trivially expanded using PPC_TLB_EPID_LOAD.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/cpu.h        |  2 --
 target/ppc/mem_helper.c | 11 ++---------
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 103bfe9dc2..8ebeaba649 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -951,8 +951,6 @@ struct ppc_radix_page_info {
  * + real/paged mode combinations. The other two modes are for
  * external PID load/store.
  */
-#define MMU_MODE8_SUFFIX _epl
-#define MMU_MODE9_SUFFIX _eps
 #define PPC_TLB_EPID_LOAD 8
 #define PPC_TLB_EPID_STORE 9
 
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 1351b53f28..56855f2381 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -177,14 +177,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr,
     } else {
         /* Slow path */
         for (i = 0; i < dcbz_size; i += 8) {
-            if (epid) {
-#if !defined(CONFIG_USER_ONLY)
-                /* Does not make sense on USER_ONLY config */
-                cpu_stq_eps_ra(env, addr + i, 0, retaddr);
-#endif
-            } else {
-                cpu_stq_data_ra(env, addr + i, 0, retaddr);
-            }
+            cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr);
         }
     }
 }
@@ -216,7 +209,7 @@ void helper_icbiep(CPUPPCState *env, target_ulong addr)
 #if !defined(CONFIG_USER_ONLY)
     /* See comments above */
     addr &= ~(env->dcache_line_size - 1);
-    cpu_ldl_epl_ra(env, addr, GETPC());
+    cpu_ldl_mmuidx_ra(env, addr, PPC_TLB_EPID_LOAD, GETPC());
 #endif
 }
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 35/41] cputlb: Remove support for MMU_MODE*_SUFFIX
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (33 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 34/41] target/ppc: " Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 36/41] cputlb: Expand cpu_ldst_template.h in cputlb.c Richard Henderson
                   ` (6 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé

All users have now been converted to cpu_*_mmuidx_ra.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h | 230 ----------------------------------------
 1 file changed, 230 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 0f3c49a005..cf4652bf48 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -271,236 +271,6 @@ void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
                        int mmu_idx, uintptr_t retaddr);
 
-#ifdef MMU_MODE0_SUFFIX
-#define CPU_MMU_INDEX 0
-#define MEMSUFFIX MMU_MODE0_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif
-
-#if (NB_MMU_MODES >= 2) && defined(MMU_MODE1_SUFFIX)
-#define CPU_MMU_INDEX 1
-#define MEMSUFFIX MMU_MODE1_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif
-
-#if (NB_MMU_MODES >= 3) && defined(MMU_MODE2_SUFFIX)
-
-#define CPU_MMU_INDEX 2
-#define MEMSUFFIX MMU_MODE2_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 3) */
-
-#if (NB_MMU_MODES >= 4) && defined(MMU_MODE3_SUFFIX)
-
-#define CPU_MMU_INDEX 3
-#define MEMSUFFIX MMU_MODE3_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 4) */
-
-#if (NB_MMU_MODES >= 5) && defined(MMU_MODE4_SUFFIX)
-
-#define CPU_MMU_INDEX 4
-#define MEMSUFFIX MMU_MODE4_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 5) */
-
-#if (NB_MMU_MODES >= 6) && defined(MMU_MODE5_SUFFIX)
-
-#define CPU_MMU_INDEX 5
-#define MEMSUFFIX MMU_MODE5_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 6) */
-
-#if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX)
-
-#define CPU_MMU_INDEX 6
-#define MEMSUFFIX MMU_MODE6_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 7) */
-
-#if (NB_MMU_MODES >= 8) && defined(MMU_MODE7_SUFFIX)
-
-#define CPU_MMU_INDEX 7
-#define MEMSUFFIX MMU_MODE7_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 8) */
-
-#if (NB_MMU_MODES >= 9) && defined(MMU_MODE8_SUFFIX)
-
-#define CPU_MMU_INDEX 8
-#define MEMSUFFIX MMU_MODE8_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 9) */
-
-#if (NB_MMU_MODES >= 10) && defined(MMU_MODE9_SUFFIX)
-
-#define CPU_MMU_INDEX 9
-#define MEMSUFFIX MMU_MODE9_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 10) */
-
-#if (NB_MMU_MODES >= 11) && defined(MMU_MODE10_SUFFIX)
-
-#define CPU_MMU_INDEX 10
-#define MEMSUFFIX MMU_MODE10_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 11) */
-
-#if (NB_MMU_MODES >= 12) && defined(MMU_MODE11_SUFFIX)
-
-#define CPU_MMU_INDEX 11
-#define MEMSUFFIX MMU_MODE11_SUFFIX
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-#endif /* (NB_MMU_MODES >= 12) */
-
-#if (NB_MMU_MODES > 12)
-#error "NB_MMU_MODES > 12 is not supported for now"
-#endif /* (NB_MMU_MODES > 12) */
-
 /* these access are slower, they must be as rare as possible */
 #define CPU_MMU_INDEX (cpu_mmu_index(env, false))
 #define MEMSUFFIX _data
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 36/41] cputlb: Expand cpu_ldst_template.h in cputlb.c
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (34 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 35/41] cputlb: Remove support for MMU_MODE*_SUFFIX Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 37/41] tcg: Search includes from the project root source directory Richard Henderson
                   ` (5 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alex Bennée, peter.maydell, Philippe Mathieu-Daudé,
	Aleksandar Markovic

Reduce the amount of preprocessor obfuscation by expanding
the text of each of the functions generated.  The result is
only slightly smaller than the original.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h          |  67 +++++++-----------
 include/exec/cpu_ldst_template.h | 117 -------------------------------
 accel/tcg/cputlb.c               | 107 +++++++++++++++++++++++++++-
 3 files changed, 130 insertions(+), 161 deletions(-)
 delete mode 100644 include/exec/cpu_ldst_template.h

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index cf4652bf48..62f38d5a22 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -94,32 +94,6 @@ typedef target_ulong abi_ptr;
 #define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
 #endif
 
-#if defined(CONFIG_USER_ONLY)
-
-extern __thread uintptr_t helper_retaddr;
-
-static inline void set_helper_retaddr(uintptr_t ra)
-{
-    helper_retaddr = ra;
-    /*
-     * Ensure that this write is visible to the SIGSEGV handler that
-     * may be invoked due to a subsequent invalid memory operation.
-     */
-    signal_barrier();
-}
-
-static inline void clear_helper_retaddr(void)
-{
-    /*
-     * Ensure that previous memory operations have succeeded before
-     * removing the data visible to the signal handler.
-     */
-    signal_barrier();
-    helper_retaddr = 0;
-}
-
-/* In user-only mode we provide only the _code and _data accessors. */
-
 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
 uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
 uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
@@ -148,6 +122,30 @@ void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
 void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
                      uint64_t val, uintptr_t retaddr);
 
+#if defined(CONFIG_USER_ONLY)
+
+extern __thread uintptr_t helper_retaddr;
+
+static inline void set_helper_retaddr(uintptr_t ra)
+{
+    helper_retaddr = ra;
+    /*
+     * Ensure that this write is visible to the SIGSEGV handler that
+     * may be invoked due to a subsequent invalid memory operation.
+     */
+    signal_barrier();
+}
+
+static inline void clear_helper_retaddr(void)
+{
+    /*
+     * Ensure that previous memory operations have succeeded before
+     * removing the data visible to the signal handler.
+     */
+    signal_barrier();
+    helper_retaddr = 0;
+}
+
 /*
  * Provide the same *_mmuidx_ra interface as for softmmu.
  * The mmu_idx argument is ignored.
@@ -271,23 +269,6 @@ void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
 void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
                        int mmu_idx, uintptr_t retaddr);
 
-/* these access are slower, they must be as rare as possible */
-#define CPU_MMU_INDEX (cpu_mmu_index(env, false))
-#define MEMSUFFIX _data
-#define DATA_SIZE 1
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 2
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 4
-#include "exec/cpu_ldst_template.h"
-
-#define DATA_SIZE 8
-#include "exec/cpu_ldst_template.h"
-#undef CPU_MMU_INDEX
-#undef MEMSUFFIX
-
 #endif /* defined(CONFIG_USER_ONLY) */
 
 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
deleted file mode 100644
index e400979f23..0000000000
--- a/include/exec/cpu_ldst_template.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- *  Software MMU support
- *
- * Generate inline load/store functions for one MMU mode and data
- * size.
- *
- * Generate a store function as well as signed and unsigned loads.
- *
- * Not used directly but included from cpu_ldst.h.
- *
- *  Copyright (c) 2003 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#if DATA_SIZE == 8
-#define SUFFIX q
-#define USUFFIX q
-#define DATA_TYPE uint64_t
-#define SHIFT 3
-#elif DATA_SIZE == 4
-#define SUFFIX l
-#define USUFFIX l
-#define DATA_TYPE uint32_t
-#define SHIFT 2
-#elif DATA_SIZE == 2
-#define SUFFIX w
-#define USUFFIX uw
-#define DATA_TYPE uint16_t
-#define DATA_STYPE int16_t
-#define SHIFT 1
-#elif DATA_SIZE == 1
-#define SUFFIX b
-#define USUFFIX ub
-#define DATA_TYPE uint8_t
-#define DATA_STYPE int8_t
-#define SHIFT 0
-#else
-#error unsupported data size
-#endif
-
-#if DATA_SIZE == 8
-#define RES_TYPE uint64_t
-#else
-#define RES_TYPE uint32_t
-#endif
-
-/* generic load/store macros */
-
-static inline RES_TYPE
-glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
-                                                  target_ulong ptr,
-                                                  uintptr_t retaddr)
-{
-    return glue(glue(cpu_ld, USUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX,
-                                                   retaddr);
-}
-
-static inline RES_TYPE
-glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
-{
-    return glue(glue(cpu_ld, USUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX, 0);
-}
-
-#if DATA_SIZE <= 2
-static inline int
-glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
-                                                  target_ulong ptr,
-                                                  uintptr_t retaddr)
-{
-    return glue(glue(cpu_lds, SUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX,
-                                                   retaddr);
-}
-
-static inline int
-glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
-{
-    return glue(glue(cpu_lds, SUFFIX), _mmuidx_ra)(env, ptr, CPU_MMU_INDEX, 0);
-}
-#endif
-
-/* generic store macro */
-
-static inline void
-glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
-                                                 target_ulong ptr,
-                                                 RES_TYPE v, uintptr_t retaddr)
-{
-    glue(glue(cpu_st, SUFFIX), _mmuidx_ra)(env, ptr, v, CPU_MMU_INDEX,
-                                           retaddr);
-}
-
-static inline void
-glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
-                                      RES_TYPE v)
-{
-    glue(glue(cpu_st, SUFFIX), _mmuidx_ra)(env, ptr, v, CPU_MMU_INDEX, 0);
-}
-
-#undef RES_TYPE
-#undef DATA_TYPE
-#undef DATA_STYPE
-#undef SUFFIX
-#undef USUFFIX
-#undef DATA_SIZE
-#undef SHIFT
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f0e4b0aee4..a991ea2964 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -35,7 +35,6 @@
 #include "qemu/atomic128.h"
 #include "translate-all.h"
 #include "trace-root.h"
-#include "qemu/plugin.h"
 #include "trace/mem.h"
 #ifdef CONFIG_PLUGIN
 #include "qemu/plugin-memory.h"
@@ -1697,6 +1696,68 @@ uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
                            ? helper_le_ldq_mmu : helper_be_ldq_mmu);
 }
 
+uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
+                          uintptr_t retaddr)
+{
+    return cpu_ldub_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
+{
+    return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_lduw_data_ra(CPUArchState *env, target_ulong ptr,
+                          uintptr_t retaddr)
+{
+    return cpu_lduw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+int cpu_ldsw_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
+{
+    return cpu_ldsw_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_ldl_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
+{
+    return cpu_ldl_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint64_t cpu_ldq_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
+{
+    return cpu_ldq_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
+}
+
+uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldub_data_ra(env, ptr, 0);
+}
+
+int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldsb_data_ra(env, ptr, 0);
+}
+
+uint32_t cpu_lduw_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_lduw_data_ra(env, ptr, 0);
+}
+
+int cpu_ldsw_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldsw_data_ra(env, ptr, 0);
+}
+
+uint32_t cpu_ldl_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldl_data_ra(env, ptr, 0);
+}
+
+uint64_t cpu_ldq_data(CPUArchState *env, target_ulong ptr)
+{
+    return cpu_ldq_data_ra(env, ptr, 0);
+}
+
 /*
  * Store Helpers
  */
@@ -1970,6 +2031,50 @@ void cpu_stq_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
     cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_TEQ);
 }
 
+void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
+                     uint32_t val, uintptr_t retaddr)
+{
+    cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stw_data_ra(CPUArchState *env, target_ulong ptr,
+                     uint32_t val, uintptr_t retaddr)
+{
+    cpu_stw_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stl_data_ra(CPUArchState *env, target_ulong ptr,
+                     uint32_t val, uintptr_t retaddr)
+{
+    cpu_stl_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stq_data_ra(CPUArchState *env, target_ulong ptr,
+                     uint64_t val, uintptr_t retaddr)
+{
+    cpu_stq_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
+}
+
+void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stb_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stw_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stw_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stl_data(CPUArchState *env, target_ulong ptr, uint32_t val)
+{
+    cpu_stl_data_ra(env, ptr, val, 0);
+}
+
+void cpu_stq_data(CPUArchState *env, target_ulong ptr, uint64_t val)
+{
+    cpu_stq_data_ra(env, ptr, val, 0);
+}
+
 /* First set of helpers allows passing in of OI and RETADDR.  This makes
    them callable from other helpers.  */
 
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 37/41] tcg: Search includes from the project root source directory
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (35 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 36/41] cputlb: Expand cpu_ldst_template.h in cputlb.c Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 38/41] tcg: Search includes in the parent " Richard Henderson
                   ` (4 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Stefan Weil, Alistair Francis, Paolo Bonzini,
	Philippe Mathieu-Daudé,
	David Gibson

From: Philippe Mathieu-Daudé <philmd@redhat.com>

We currently search both the root and the tcg/ directories for tcg
files:

  $ git grep '#include "tcg/' | wc -l
  28

  $ git grep '#include "tcg[^/]' | wc -l
  94

To simplify the preprocessor search path, unify by expliciting the
tcg/ directory.

Patch created mechanically by running:

  $ for x in \
      tcg.h tcg-mo.h tcg-op.h tcg-opc.h \
      tcg-op-gvec.h tcg-gvec-desc.h; do \
    sed -i "s,#include \"$x\",#include \"tcg/$x\"," \
      $(git grep -l "#include \"$x\""); \
    done

Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts)
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200101112303.20724-2-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu_ldst.h       | 2 +-
 tcg/i386/tcg-target.h         | 2 +-
 tcg/tcg-op.h                  | 2 +-
 tcg/tcg.h                     | 4 ++--
 accel/tcg/cpu-exec.c          | 2 +-
 accel/tcg/tcg-runtime-gvec.c  | 2 +-
 accel/tcg/tcg-runtime.c       | 2 +-
 accel/tcg/translate-all.c     | 2 +-
 accel/tcg/user-exec.c         | 2 +-
 bsd-user/main.c               | 2 +-
 cpus.c                        | 2 +-
 exec.c                        | 2 +-
 linux-user/main.c             | 2 +-
 linux-user/syscall.c          | 2 +-
 target/alpha/translate.c      | 2 +-
 target/arm/helper-a64.c       | 2 +-
 target/arm/sve_helper.c       | 2 +-
 target/arm/translate-a64.c    | 4 ++--
 target/arm/translate-sve.c    | 6 +++---
 target/arm/translate.c        | 4 ++--
 target/cris/translate.c       | 2 +-
 target/hppa/translate.c       | 2 +-
 target/i386/mem_helper.c      | 2 +-
 target/i386/translate.c       | 2 +-
 target/lm32/translate.c       | 2 +-
 target/m68k/translate.c       | 2 +-
 target/microblaze/translate.c | 2 +-
 target/mips/translate.c       | 2 +-
 target/moxie/translate.c      | 2 +-
 target/nios2/translate.c      | 2 +-
 target/openrisc/translate.c   | 2 +-
 target/ppc/mem_helper.c       | 2 +-
 target/ppc/translate.c        | 4 ++--
 target/riscv/cpu_helper.c     | 2 +-
 target/riscv/translate.c      | 2 +-
 target/s390x/mem_helper.c     | 2 +-
 target/s390x/translate.c      | 4 ++--
 target/sh4/translate.c        | 2 +-
 target/sparc/ldst_helper.c    | 2 +-
 target/sparc/translate.c      | 2 +-
 target/tilegx/translate.c     | 2 +-
 target/tricore/translate.c    | 2 +-
 target/unicore32/translate.c  | 2 +-
 target/xtensa/translate.c     | 2 +-
 tcg/optimize.c                | 2 +-
 tcg/tcg-common.c              | 2 +-
 tcg/tcg-op-gvec.c             | 8 ++++----
 tcg/tcg-op-vec.c              | 6 +++---
 tcg/tcg-op.c                  | 6 +++---
 tcg/tcg.c                     | 2 +-
 tcg/tci.c                     | 2 +-
 51 files changed, 65 insertions(+), 65 deletions(-)

diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 62f38d5a22..a46116167c 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -214,7 +214,7 @@ static inline void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
 #else
 
 /* Needed for TCG_OVERSIZED_GUEST */
-#include "tcg.h"
+#include "tcg/tcg.h"
 
 static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
 {
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 928e8b87bb..bfb3f5f6e9 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -223,7 +223,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
  * The x86 has a pretty strong memory ordering which only really
  * allows for some stores to be re-ordered after loads.
  */
-#include "tcg-mo.h"
+#include "tcg/tcg-mo.h"
 
 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
 
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 4af272daa5..230db6e022 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -25,7 +25,7 @@
 #ifndef TCG_TCG_OP_H
 #define TCG_TCG_OP_H
 
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 3b4f79301c..54e5446880 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -31,7 +31,7 @@
 #include "qemu/bitops.h"
 #include "qemu/plugin.h"
 #include "qemu/queue.h"
-#include "tcg-mo.h"
+#include "tcg/tcg-mo.h"
 #include "tcg-target.h"
 #include "qemu/int128.h"
 
@@ -211,7 +211,7 @@ typedef uint64_t TCGRegSet;
 
 typedef enum TCGOpcode {
 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
-#include "tcg-opc.h"
+#include "tcg/tcg-opc.h"
 #undef DEF
     NB_OPS,
 } TCGOpcode;
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 62068d10c3..2560c90eec 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -23,7 +23,7 @@
 #include "trace.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "qemu/atomic.h"
 #include "sysemu/qtest.h"
 #include "qemu/timer.h"
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 51cb29ca79..5b1902d591 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -21,7 +21,7 @@
 #include "qemu/host-utils.h"
 #include "cpu.h"
 #include "exec/helper-proto.h"
-#include "tcg-gvec-desc.h"
+#include "tcg/tcg-gvec-desc.h"
 
 
 /* Virtually all hosts support 16-byte vectors.  Those that don't can emulate
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 4ab2cf7f75..446465a09a 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -30,7 +30,7 @@
 #include "exec/tb-lookup.h"
 #include "disas/disas.h"
 #include "exec/log.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 
 /* 32-bit helpers */
 
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 7749c3dda5..1e9b2b6a62 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -25,7 +25,7 @@
 #include "trace.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #if defined(CONFIG_USER_ONLY)
 #include "qemu.h"
 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 79da4219bb..4be78eb9b3 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -20,7 +20,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "qemu/bitops.h"
 #include "exec/cpu_ldst.h"
 #include "translate-all.h"
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 7f4e3cd627..770c2b267a 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -33,7 +33,7 @@
 #include "qemu/module.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "qemu/timer.h"
 #include "qemu/envlist.h"
 #include "exec/log.h"
diff --git a/cpus.c b/cpus.c
index b472378b70..18f56572fa 100644
--- a/cpus.c
+++ b/cpus.c
@@ -53,7 +53,7 @@
 #include "qemu/bitmap.h"
 #include "qemu/seqlock.h"
 #include "qemu/guest-random.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "hw/nmi.h"
 #include "sysemu/replay.h"
 #include "sysemu/runstate.h"
diff --git a/exec.c b/exec.c
index d4b769d0d4..0f6b087f57 100644
--- a/exec.c
+++ b/exec.c
@@ -25,7 +25,7 @@
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "exec/target_page.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "hw/qdev-core.h"
 #include "hw/qdev-properties.h"
 #if !defined(CONFIG_USER_ONLY)
diff --git a/linux-user/main.c b/linux-user/main.c
index 8718d03ee2..fba833aac9 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -37,7 +37,7 @@
 #include "qemu/plugin.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "qemu/timer.h"
 #include "qemu/envlist.h"
 #include "qemu/guest-random.h"
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 34825f15bf..249e4b95fc 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -115,7 +115,7 @@
 #include "user/syscall-trace.h"
 #include "qapi/error.h"
 #include "fd-trans.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 
 #ifndef CLONE_IO
 #define CLONE_IO                0x80000000      /* Clone io context */
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index f7f1ed0f41..8870284f57 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -23,7 +23,7 @@
 #include "disas/disas.h"
 #include "qemu/host-utils.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index b4cd680fc4..36aa6badfd 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -31,7 +31,7 @@
 #include "exec/cpu_ldst.h"
 #include "qemu/int128.h"
 #include "qemu/atomic128.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "fpu/softfloat.h"
 #include <zlib.h> /* For crc32 */
 
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 83cc7f5bb5..fdfa652094 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -25,7 +25,7 @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "fpu/softfloat.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 
 
 /* Note that vector data is stored in host-endian 64-bit chunks,
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d4bebbe629..a1d4dce4fa 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -20,8 +20,8 @@
 
 #include "cpu.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
-#include "tcg-op-gvec.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
 #include "qemu/log.h"
 #include "arm_ldst.h"
 #include "translate.h"
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 5d7edd0907..b35bad245e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -20,9 +20,9 @@
 #include "qemu/osdep.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
-#include "tcg-op-gvec.h"
-#include "tcg-gvec-desc.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "tcg/tcg-gvec-desc.h"
 #include "qemu/log.h"
 #include "arm_ldst.h"
 #include "translate.h"
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2b6c1f91bf..39821d040b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -24,8 +24,8 @@
 #include "internals.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
-#include "tcg-op-gvec.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
 #include "qemu/log.h"
 #include "qemu/bitops.h"
 #include "arm_ldst.h"
diff --git a/target/cris/translate.c b/target/cris/translate.c
index cb57516a44..aaa46b5bca 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -27,7 +27,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/helper-proto.h"
 #include "mmu.h"
 #include "exec/cpu_ldst.h"
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 2f8d407a82..f25927aeca 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -22,7 +22,7 @@
 #include "disas/disas.h"
 #include "qemu/host-utils.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c
index d50d4b0c40..acf41f8885 100644
--- a/target/i386/mem_helper.c
+++ b/target/i386/mem_helper.c
@@ -24,7 +24,7 @@
 #include "exec/cpu_ldst.h"
 #include "qemu/int128.h"
 #include "qemu/atomic128.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 
 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0)
 {
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 7c99ef1385..d9af8f4078 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -22,7 +22,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "exec/translator.h"
 
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 73db9654d6..e583d52d03 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -23,7 +23,7 @@
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
 #include "exec/translator.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "qemu/qemu-print.h"
 
 #include "exec/cpu_ldst.h"
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index fcdb7bc8e4..31b743717e 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -22,7 +22,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "qemu/log.h"
 #include "qemu/qemu-print.h"
 #include "exec/cpu_ldst.h"
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 525115b041..37a844db99 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -22,7 +22,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/helper-proto.h"
 #include "microblaze-decode.h"
 #include "exec/cpu_ldst.h"
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4bff585bd6..efe75e6be0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26,7 +26,7 @@
 #include "internal.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "hw/mips/cpudevs.h"
 
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index c87e9ec2b1..d5fb27dfb8 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -26,7 +26,7 @@
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "disas/disas.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "qemu/qemu-print.h"
 
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 82107bf270..6c34cd3193 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -23,7 +23,7 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/exec-all.h"
 #include "disas/disas.h"
 #include "exec/helper-proto.h"
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 8dd28d6cf1..52323a16df 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -22,7 +22,7 @@
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "disas/disas.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "qemu/log.h"
 #include "qemu/bitops.h"
 #include "qemu/qemu-print.h"
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 56855f2381..e8e2a8ac2a 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -25,7 +25,7 @@
 #include "exec/helper-proto.h"
 #include "helper_regs.h"
 #include "exec/cpu_ldst.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "internal.h"
 #include "qemu/atomic128.h"
 
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f5fe5d0611..9dcf8dc261 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -23,8 +23,8 @@
 #include "internal.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
-#include "tcg-op-gvec.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
 #include "qemu/host-utils.h"
 #include "qemu/main-loop.h"
 #include "exec/cpu_ldst.h"
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 767c8762ac..85403da9c8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -22,7 +22,7 @@
 #include "qemu/main-loop.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "trace.h"
 
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ab6a891dc3..56b1b1fe7b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -19,7 +19,7 @@
 #include "qemu/osdep.h"
 #include "qemu/log.h"
 #include "cpu.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "disas/disas.h"
 #include "exec/cpu_ldst.h"
 #include "exec/exec-all.h"
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 428bde4c54..a237dec757 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -27,7 +27,7 @@
 #include "exec/cpu_ldst.h"
 #include "qemu/int128.h"
 #include "qemu/atomic128.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/s390x/storage-keys.h"
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 4292bb0dd0..b764ec3140 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -33,8 +33,8 @@
 #include "internal.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
-#include "tcg-op-gvec.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
 #include "qemu/log.h"
 #include "qemu/host-utils.h"
 #include "exec/cpu_ldst.h"
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 922785e225..6192d83e8c 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -23,7 +23,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 7345827a96..e91cfdecd3 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -19,7 +19,7 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "tcg.h"
+#include "tcg/tcg.h"
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index edc23a7c40..9416a551cf 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -24,7 +24,7 @@
 #include "disas/disas.h"
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 
 #include "exec/helper-gen.h"
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index abce7e1c75..65f1c91f4f 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -24,7 +24,7 @@
 #include "exec/log.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "linux-user/syscall_defs.h"
 
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c574638c9f..609d75ae8a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -22,7 +22,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "exec/cpu_ldst.h"
 #include "qemu/qemu-print.h"
 
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 0f6891b8aa..d4b06df672 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -13,7 +13,7 @@
 #include "cpu.h"
 #include "disas/disas.h"
 #include "exec/exec-all.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "qemu/log.h"
 #include "exec/cpu_ldst.h"
 #include "exec/translator.h"
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index e6d910786c..8aa972cafd 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -33,7 +33,7 @@
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "disas/disas.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 #include "qemu/log.h"
 #include "qemu/qemu-print.h"
 #include "exec/cpu_ldst.h"
diff --git a/tcg/optimize.c b/tcg/optimize.c
index f7f4e873c9..53aa8e5329 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -24,7 +24,7 @@
  */
 
 #include "qemu/osdep.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 
 #define CASE_OP_32_64(x)                        \
         glue(glue(case INDEX_op_, x), _i32):    \
diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c
index 97305a3efc..7e1992e79e 100644
--- a/tcg/tcg-common.c
+++ b/tcg/tcg-common.c
@@ -32,7 +32,7 @@ uintptr_t tci_tb_ptr;
 TCGOpDef tcg_op_defs[] = {
 #define DEF(s, oargs, iargs, cargs, flags) \
          { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
-#include "tcg-opc.h"
+#include "tcg/tcg-opc.h"
 #undef DEF
 };
 const size_t tcg_op_defs_max = ARRAY_SIZE(tcg_op_defs);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 5c95ecd51c..41b4a3c661 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -18,11 +18,11 @@
  */
 
 #include "qemu/osdep.h"
-#include "tcg.h"
-#include "tcg-op.h"
-#include "tcg-op-gvec.h"
+#include "tcg/tcg.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
 #include "qemu/main-loop.h"
-#include "tcg-gvec-desc.h"
+#include "tcg/tcg-gvec-desc.h"
 
 #define MAX_UNROLL  4
 
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 6714991bf4..b6937e8d64 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -19,9 +19,9 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "tcg.h"
-#include "tcg-op.h"
-#include "tcg-mo.h"
+#include "tcg/tcg.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-mo.h"
 
 /* Reduce the number of ifdefs below.  This assumes that all uses of
    TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c245126f98..7d782002e3 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -25,9 +25,9 @@
 #include "qemu/osdep.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
-#include "tcg.h"
-#include "tcg-op.h"
-#include "tcg-mo.h"
+#include "tcg/tcg.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-mo.h"
 #include "trace-tcg.h"
 #include "trace/mem.h"
 #include "exec/plugin-gen.h"
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4f616ba38b..dd4b3d7684 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -48,7 +48,7 @@
 #include "hw/boards.h"
 #endif
 
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 
 #if UINTPTR_MAX == UINT32_MAX
 # define ELF_CLASS  ELFCLASS32
diff --git a/tcg/tci.c b/tcg/tci.c
index a6208653e8..46fe9ce63f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -30,7 +30,7 @@
 #include "qemu-common.h"
 #include "tcg/tcg.h"           /* MAX_OPC_PARAM_IARGS */
 #include "exec/cpu_ldst.h"
-#include "tcg-op.h"
+#include "tcg/tcg-op.h"
 
 /* Marker for missing code. */
 #define TODO() \
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 38/41] tcg: Search includes in the parent source directory
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (36 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 37/41] tcg: Search includes from the project root source directory Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 39/41] tcg: Move TCG headers to include/tcg/ Richard Henderson
                   ` (3 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Stefan Weil, Alistair Francis, Paolo Bonzini,
	Philippe Mathieu-Daudé,
	David Gibson

From: Philippe Mathieu-Daudé <philmd@redhat.com>

All the *.inc.c files included by tcg/$TARGET/tcg-target.inc.c
are in tcg/, their parent directory. To simplify the preprocessor
search path, include the relative parent path: '..'.

Patch created mechanically by running:

  $ for x in tcg-pool.inc.c tcg-ldst.inc.c; do \
    sed -i "s,#include \"$x\",#include \"../$x\"," \
      $(git grep -l "#include \"$x\""); \
    done

Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc parts)
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200101112303.20724-3-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.inc.c | 4 ++--
 tcg/arm/tcg-target.inc.c     | 4 ++--
 tcg/i386/tcg-target.inc.c    | 4 ++--
 tcg/mips/tcg-target.inc.c    | 2 +-
 tcg/ppc/tcg-target.inc.c     | 4 ++--
 tcg/riscv/tcg-target.inc.c   | 4 ++--
 tcg/s390/tcg-target.inc.c    | 4 ++--
 tcg/sparc/tcg-target.inc.c   | 2 +-
 8 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 3f921015d3..843fd0ca69 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -10,7 +10,7 @@
  * See the COPYING file in the top-level directory for details.
  */
 
-#include "tcg-pool.inc.c"
+#include "../tcg-pool.inc.c"
 #include "qemu/bitops.h"
 
 /* We're going to re-use TCGType in setting of the SF bit, which controls
@@ -1541,7 +1541,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
 }
 
 #ifdef CONFIG_SOFTMMU
-#include "tcg-ldst.inc.c"
+#include "../tcg-ldst.inc.c"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     TCGMemOpIdx oi, uintptr_t ra)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 94d80d79d1..fffb6611e2 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -23,7 +23,7 @@
  */
 
 #include "elf.h"
-#include "tcg-pool.inc.c"
+#include "../tcg-pool.inc.c"
 
 int arm_arch = __ARM_ARCH;
 
@@ -1131,7 +1131,7 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
 }
 
 #ifdef CONFIG_SOFTMMU
-#include "tcg-ldst.inc.c"
+#include "../tcg-ldst.inc.c"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     int mmu_idx, uintptr_t ra)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 9d8ed974e0..cdedcb2b25 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -22,7 +22,7 @@
  * THE SOFTWARE.
  */
 
-#include "tcg-pool.inc.c"
+#include "../tcg-pool.inc.c"
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@@ -1647,7 +1647,7 @@ static void tcg_out_nopn(TCGContext *s, int n)
 }
 
 #if defined(CONFIG_SOFTMMU)
-#include "tcg-ldst.inc.c"
+#include "../tcg-ldst.inc.c"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     int mmu_idx, uintptr_t ra)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 5442167045..1da663ce84 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -1107,7 +1107,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
 }
 
 #if defined(CONFIG_SOFTMMU)
-#include "tcg-ldst.inc.c"
+#include "../tcg-ldst.inc.c"
 
 static void * const qemu_ld_helpers[16] = {
     [MO_UB]   = helper_ret_ldub_mmu,
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index d308d69aba..ee1f9227c1 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -23,7 +23,7 @@
  */
 
 #include "elf.h"
-#include "tcg-pool.inc.c"
+#include "../tcg-pool.inc.c"
 
 #if defined _CALL_DARWIN || defined __APPLE__
 #define TCG_TARGET_CALL_DARWIN
@@ -1845,7 +1845,7 @@ static const uint32_t qemu_exts_opc[4] = {
 };
 
 #if defined (CONFIG_SOFTMMU)
-#include "tcg-ldst.inc.c"
+#include "../tcg-ldst.inc.c"
 
 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
  *                                 int mmu_idx, uintptr_t ra)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 7018509693..2bc0ba71f2 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -27,7 +27,7 @@
  * THE SOFTWARE.
  */
 
-#include "tcg-pool.inc.c"
+#include "../tcg-pool.inc.c"
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@@ -921,7 +921,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
  */
 
 #if defined(CONFIG_SOFTMMU)
-#include "tcg-ldst.inc.c"
+#include "../tcg-ldst.inc.c"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     TCGMemOpIdx oi, uintptr_t ra)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 8aaa4cebe8..b07e9ff7d6 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -29,7 +29,7 @@
 #error "unsupported code generation mode"
 #endif
 
-#include "tcg-pool.inc.c"
+#include "../tcg-pool.inc.c"
 #include "elf.h"
 
 /* ??? The translation blocks produced by TCG are generally small enough to
@@ -1536,7 +1536,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
 }
 
 #if defined(CONFIG_SOFTMMU)
-#include "tcg-ldst.inc.c"
+#include "../tcg-ldst.inc.c"
 
 /* We're expecting to use a 20-bit negative offset on the tlb memory ops.  */
 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index d7986cda5c..65fddb310d 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -22,7 +22,7 @@
  * THE SOFTWARE.
  */
 
-#include "tcg-pool.inc.c"
+#include "../tcg-pool.inc.c"
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 39/41] tcg: Move TCG headers to include/tcg/
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (37 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 38/41] tcg: Search includes in the parent " Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 40/41] configure: Remove tcg/ from the preprocessor include search list Richard Henderson
                   ` (2 subsequent siblings)
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Alistair Francis, Philippe Mathieu-Daudé,
	Stefan Weil, Paolo Bonzini

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200101112303.20724-4-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 {tcg => include/tcg}/tcg-gvec-desc.h | 0
 {tcg => include/tcg}/tcg-mo.h        | 0
 {tcg => include/tcg}/tcg-op-gvec.h   | 0
 {tcg => include/tcg}/tcg-op.h        | 0
 {tcg => include/tcg}/tcg-opc.h       | 0
 {tcg => include/tcg}/tcg.h           | 0
 MAINTAINERS                          | 1 +
 7 files changed, 1 insertion(+)
 rename {tcg => include/tcg}/tcg-gvec-desc.h (100%)
 rename {tcg => include/tcg}/tcg-mo.h (100%)
 rename {tcg => include/tcg}/tcg-op-gvec.h (100%)
 rename {tcg => include/tcg}/tcg-op.h (100%)
 rename {tcg => include/tcg}/tcg-opc.h (100%)
 rename {tcg => include/tcg}/tcg.h (100%)

diff --git a/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h
similarity index 100%
rename from tcg/tcg-gvec-desc.h
rename to include/tcg/tcg-gvec-desc.h
diff --git a/tcg/tcg-mo.h b/include/tcg/tcg-mo.h
similarity index 100%
rename from tcg/tcg-mo.h
rename to include/tcg/tcg-mo.h
diff --git a/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
similarity index 100%
rename from tcg/tcg-op-gvec.h
rename to include/tcg/tcg-op-gvec.h
diff --git a/tcg/tcg-op.h b/include/tcg/tcg-op.h
similarity index 100%
rename from tcg/tcg-op.h
rename to include/tcg/tcg-op.h
diff --git a/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
similarity index 100%
rename from tcg/tcg-opc.h
rename to include/tcg/tcg-opc.h
diff --git a/tcg/tcg.h b/include/tcg/tcg.h
similarity index 100%
rename from tcg/tcg.h
rename to include/tcg/tcg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index cd2dc137a3..1c6919c455 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2386,6 +2386,7 @@ Common TCG code
 M: Richard Henderson <rth@twiddle.net>
 S: Maintained
 F: tcg/
+F: include/tcg/
 
 TCG Plugins
 M: Alex Bennée <alex.bennee@linaro.org>
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 40/41] configure: Remove tcg/ from the preprocessor include search list
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (38 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 39/41] tcg: Move TCG headers to include/tcg/ Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-08  3:45 ` [PULL 41/41] MAINTAINERS: Replace Claudio Fontana for tcg/aarch64 Richard Henderson
  2020-01-10 15:51 ` [PULL 00/41] tcg patch queue Peter Maydell
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Alistair Francis, Philippe Mathieu-Daudé,
	Stefan Weil, Paolo Bonzini

From: Philippe Mathieu-Daudé <philmd@redhat.com>

All tcg includes are relative to the repository root directory,
we can safely remove the tcg/ directory from the include search
path list.

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200101112303.20724-5-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configure | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configure b/configure
index 94a4b1c848..cac36a9e08 100755
--- a/configure
+++ b/configure
@@ -7386,7 +7386,6 @@ elif test "$ARCH" = "riscv32" || test "$ARCH" = "riscv64" ; then
 else
   QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES"
 fi
-QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg $QEMU_INCLUDES"
 
 echo "TOOLS=$tools" >> $config_host_mak
 echo "ROMS=$roms" >> $config_host_mak
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PULL 41/41] MAINTAINERS: Replace Claudio Fontana for tcg/aarch64
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (39 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 40/41] configure: Remove tcg/ from the preprocessor include search list Richard Henderson
@ 2020-01-08  3:45 ` Richard Henderson
  2020-01-10 15:51 ` [PULL 00/41] tcg patch queue Peter Maydell
  41 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-08  3:45 UTC (permalink / raw)
  To: qemu-devel
  Cc: peter.maydell, Alex Bennée, Claudio Fontana,
	Philippe Mathieu-Daudé

Claudio's Huawei address has been defunct for quite a while.  In

  https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg06872.html

he asked for his personal address to be removed as well.

I will take over officially.

Cc: Claudio Fontana <claudio.fontana@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 MAINTAINERS | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1c6919c455..dcb46db5e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2396,8 +2396,7 @@ F: plugins/
 F: tests/plugin
 
 AArch64 TCG target
-M: Claudio Fontana <claudio.fontana@huawei.com>
-M: Claudio Fontana <claudio.fontana@gmail.com>
+M: Richard Henderson <richard.henderson@linaro.org>
 S: Maintained
 L: qemu-arm@nongnu.org
 F: tcg/aarch64/
-- 
2.20.1



^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 00/41] tcg patch queue
  2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
                   ` (40 preceding siblings ...)
  2020-01-08  3:45 ` [PULL 41/41] MAINTAINERS: Replace Claudio Fontana for tcg/aarch64 Richard Henderson
@ 2020-01-10 15:51 ` Peter Maydell
  2020-01-13 21:10   ` Richard Henderson
  41 siblings, 1 reply; 51+ messages in thread
From: Peter Maydell @ 2020-01-10 15:51 UTC (permalink / raw)
  To: Richard Henderson; +Cc: QEMU Developers

On Wed, 8 Jan 2020 at 03:45, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 035eed4c0d257c905a556fa0f4865a0c077b4e7f:
>
>   Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request' into staging (2020-01-07 17:08:21 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/rth7680/qemu.git tags/pull-tcg-20200108
>
> for you to fetch changes up to 5e7ef51cbe47e726f76bfbc208e167085cf398c4:
>
>   MAINTAINERS: Replace Claudio Fontana for tcg/aarch64 (2020-01-08 11:54:12 +1100)
>
> ----------------------------------------------------------------
> Improve -static and -pie linking
> Add cpu_{ld,st}*_mmuidx_ra
> Remove MMU_MODE*_SUFFIX
> Move tcg headers under include/

This makes the x86-64 'ls' binary in the linux-user-tests
tarball segfault:

/home/petmay01/linaro/qemu-for-merges/build/all-linux-static/x86_64-linux-user/qemu-x86_64
-L ./gnemul/qemu-x86_64 x86_64/ls -l dummyfile
qemu: uncaught target signal 11 (Segmentation fault) - core dumped

(probably
http://people.linaro.org/~peter.maydell/linux-user-test-modified-pmm.tgz
if you don't have a copy to hand)

thanks
-- PMM


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 00/41] tcg patch queue
  2020-01-10 15:51 ` [PULL 00/41] tcg patch queue Peter Maydell
@ 2020-01-13 21:10   ` Richard Henderson
  2020-01-13 21:50     ` Richard Henderson
  0 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2020-01-13 21:10 UTC (permalink / raw)
  To: Peter Maydell; +Cc: QEMU Developers

On 1/10/20 5:51 AM, Peter Maydell wrote:
>> Improve -static and -pie linking
>> Add cpu_{ld,st}*_mmuidx_ra
>> Remove MMU_MODE*_SUFFIX
>> Move tcg headers under include/
> 
> This makes the x86-64 'ls' binary in the linux-user-tests
> tarball segfault:
> 
> /home/petmay01/linaro/qemu-for-merges/build/all-linux-static/x86_64-linux-user/qemu-x86_64
> -L ./gnemul/qemu-x86_64 x86_64/ls -l dummyfile
> qemu: uncaught target signal 11 (Segmentation fault) - core dumped
> 
> (probably
> http://people.linaro.org/~peter.maydell/linux-user-test-modified-pmm.tgz
> if you don't have a copy to hand)

I do have a copy, and it works for me.  I tried with a rebase vs master, just
in case, and don't see it there either.

Details of this test system?

I suppose I'll grab your tarball just to see if the binaries are different...


r~


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 00/41] tcg patch queue
  2020-01-13 21:10   ` Richard Henderson
@ 2020-01-13 21:50     ` Richard Henderson
  2020-01-13 22:06       ` Richard Henderson
  0 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2020-01-13 21:50 UTC (permalink / raw)
  To: Peter Maydell; +Cc: QEMU Developers

On 1/13/20 11:10 AM, Richard Henderson wrote:
> Details of this test system?
> 
> I suppose I'll grab your tarball just to see if the binaries are different...

Ho hum.  Something is different.  I reproduce the problem with your tarball.


r~


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 00/41] tcg patch queue
  2020-01-13 21:50     ` Richard Henderson
@ 2020-01-13 22:06       ` Richard Henderson
  2020-01-14  1:16         ` Richard Henderson
  0 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2020-01-13 22:06 UTC (permalink / raw)
  To: Peter Maydell; +Cc: QEMU Developers

On 1/13/20 11:50 AM, Richard Henderson wrote:
> On 1/13/20 11:10 AM, Richard Henderson wrote:
>> Details of this test system?
>>
>> I suppose I'll grab your tarball just to see if the binaries are different...
> 
> Ho hum.  Something is different.  I reproduce the problem with your tarball.

Well, yes and no.  Your tarball also fails for me with master, v4.2.0, and
v4.1.1, so I can't see how I can trust it at all.

Thoughts?


r~


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 00/41] tcg patch queue
  2020-01-13 22:06       ` Richard Henderson
@ 2020-01-14  1:16         ` Richard Henderson
  0 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2020-01-14  1:16 UTC (permalink / raw)
  To: Peter Maydell; +Cc: QEMU Developers

On 1/13/20 12:06 PM, Richard Henderson wrote:
> On 1/13/20 11:50 AM, Richard Henderson wrote:
>> On 1/13/20 11:10 AM, Richard Henderson wrote:
>>> Details of this test system?
>>>
>>> I suppose I'll grab your tarball just to see if the binaries are different...
>>
>> Ho hum.  Something is different.  I reproduce the problem with your tarball.
> 
> Well, yes and no.  Your tarball also fails for me with master, v4.2.0, and
> v4.1.1, so I can't see how I can trust it at all.

One final note for today -- your tarball works for me on all branches
(tcg-next, master, v4.2.0) on Centos 7.

I was previously using my desktop, Ubuntu 19.10.

So, there's certainly something odd going on...


r~


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
  2020-01-08  3:45 ` [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX Richard Henderson
@ 2020-02-01 20:12   ` Philippe Mathieu-Daudé
  2020-02-01 22:07     ` Philippe Mathieu-Daudé
  2020-02-02  9:20     ` Thomas Huth
  0 siblings, 2 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-01 20:12 UTC (permalink / raw)
  To: Richard Henderson, Alex Bennée
  Cc: peter.maydell, David Hildenbrand, qemu-devel,
	Aleksandar Markovic, Aleksandar Rikalo,
	Philippe Mathieu-Daudé,
	Aurelien Jarno

Hi Richard,

On 1/8/20 4:45 AM, Richard Henderson wrote:
> The separate suffixed functions were used to construct
> some do_##insn function switched on mmu_idx.  The interface
> is exactly identical to the *_mmuidx_ra functions.  Replace
> them directly and remove the constructions.
> 
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>

I'm seeing a regression since commit 7dd547e5a (however I'm not sure
this particular commit introduced the regression, or instead revealed it).

I get a hang when booting a I6400 CPU on Malta:

$ qemu-system-mips64el -cpu I6400 -serial stdio \
  -kernel vmlinux \
  -append "clocksource=GIC console=ttyS0 printk.time=1"
Linux version 4.7.0-rc1 (@859affe05464) (gcc version 6.3.0 20170516
(Debian 6.3.0-18) ) #2 SMP Sat Feb 1 18:16:17 UTC 2020
GCRs appear to have been moved (expected them at 0x1fbf8000)!
earlycon: uart8250 at I/O port 0x3f8 (options '38400n8')
bootconsole [uart8250] enabled
MIPS CPS SMP unable to proceed without a CM
CPU0 revision is: 0001a900 (MIPS I6400)
FPU revision is: 20f30300
MSA revision is: 00000300
MIPS: machine is mti,malta
Software DMA cache coherency enabled
Determined physical RAM map:
 memory: 0000000008000000 @ 0000000000000000 (usable)
Zone ranges:
  DMA      [mem 0x0000000000000000-0x0000000000ffffff]
  DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
  Normal   empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x0000000007ffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 64 bytes
percpu: Embedded 5 pages/cpu @980000000107c000 s29664 r8192 d44064 u81920
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8163
Kernel command line: clocksource=GIC console=ttyS0 printk.time=1
[    0.000000] PID hash table entries: 512 (order: -2, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 3, 131072
bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 2, 65536 bytes)
[    0.000000] Writing ErrCtl register=00000000
[    0.000000] Readback ErrCtl register=00000000
[    0.000000] MAAR configuration:
[    0.000000]   [0]: 0x0000000000010000-0x0000000007ffffff speculate
[    0.000000]   [1]: disabled
[    0.000000]   [2]: disabled
[    0.000000]   [3]: disabled
[    0.000000]   [4]: disabled
[    0.000000]   [5]: disabled
[    0.000000]   [6]: disabled
[    0.000000]   [7]: disabled
[    0.000000] Memory: 121728K/131072K available (5253K kernel code,
380K rwdata, 1276K rodata, 304K init, 278K bss, 9344K reserved, 0K
cma-reserved)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 64.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=1
[    0.000000] NR_IRQS:256
[    0.000000] CPU frequency 200.00 MHz
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112598155 ns
[    0.000223] sched_clock: 32 bits at 100MHz, resolution 9ns, wraps
every 21474829307ns
[    0.008011] Console: colour dummy device 80x25
[    0.012181] Calibrating delay loop... 950.27 BogoMIPS (lpj=4751360)
[    0.164015] pid_max: default: 32768 minimum: 301
[    0.165920] Mount-cache hash table entries: 2048 (order: 0, 16384 bytes)
[    0.166244] Mountpoint-cache hash table entries: 2048 (order: 0,
16384 bytes)
[    0.202498] Brought up 1 CPUs
[    0.213199] devtmpfs: initialized
[    0.228877] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.236181] NET: Registered protocol family 16
[    0.253496] clocksource: pit: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 1601818034827 ns
[    0.254012] pm-cps: no CM, non-coherent states unavailable
[    0.257508] ------------[ cut here ]------------
[    0.258085] WARNING: CPU: 0 PID: 1 at fs/kernfs/dir.c:502
__kernfs_remove+0x250/0x258
[    0.258489] Modules linked in:
[   21.494186] INFO: rcu_sched detected stalls on CPUs/tasks:
[   21.494530]  (detected by 0, t=2102 jiffies, g=-299, c=-300, q=1)
[   21.494921] All QSes seen, last rcu_sched kthread activity 2101
(4294939419-4294937318), jiffies_till_next_fqs=1, root ->qsmask 0x0
[   21.495583] swapper/0       R  running task        0     1      0
0x00100004
[   21.496028] Stack : 000000000000001d 0000000000000004
ffffffff80790000 ffffffff80820000
          0000000000000000 0000000000000000 000000000000001d
0000000000000002
          ffffffff80820000 ffffffff80170c70 0000000000000000
0000000000000000
          0000000000000000 ffffffff80822328 0000000000000001
ffffffff80822328
          9800000007052fc0 ffffffff80780000 ffffffff8078e340
ffffffff8078e340
          ffffffff80780000 ffffffff80780000 ffffffff80781010
ffffffff8078e540
          0000000000000000 0000000000000000 0000000000000000
0000000000000000
          0000000000000000 98000000070577b0 0000000000000000
ffffffff80182a64
          0000000000000000 0000000000000000 0000000000100004
9800000007052fc0
          ffffffff80780000 ffffffff8010c460 9800000001082f80
ffffffff80182a64
          ...
[   21.498954] Call Trace:
[   21.499132] [<ffffffff8010c460>] show_stack+0x80/0xa0
[   21.499520] [<ffffffff80182a64>] rcu_check_callbacks+0x804/0x810
[   21.499744] [<ffffffff80185360>] update_process_times+0x38/0x70
[   21.499981] [<ffffffff80193c34>] tick_handle_periodic+0x2c/0xa8
[   21.500215] [<ffffffff801114b4>] c0_compare_interrupt+0x74/0xb8
[   21.500451] [<ffffffff80172e18>] handle_irq_event_percpu+0x80/0x1a0
[   21.500707] [<ffffffff801775ac>] handle_percpu_irq+0x7c/0xb8
[   21.500935] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
[   21.501176] [<ffffffff80108010>] do_IRQ+0x18/0x28
[   21.501369] [<ffffffff803746c4>] plat_irq_dispatch+0x64/0xa0
[   21.501606] [<ffffffff80106370>] ret_from_irq+0x0/0x4
[   21.501868] [<ffffffff8034573c>] dump_stack+0x6c/0xd0
[   21.502068] [<ffffffff8012d088>] __warn+0xf0/0x108
[   21.502268] [<ffffffff80269e78>] __kernfs_remove+0x250/0x258
[   21.502519] [<ffffffff8026ae38>] kernfs_remove_by_name_ns+0x48/0xb0
[   21.502771] [<ffffffff8026dc44>] remove_files.isra.0+0x44/0x98
[   21.503003] [<ffffffff8026e034>] sysfs_remove_group+0x4c/0xc0
[   21.503339] [<ffffffff807cbc18>] param_sysfs_init+0x178/0x1f0
[   21.503605] [<ffffffff80100564>] do_one_initcall+0x3c/0x148
[   21.503830] [<ffffffff807c4b38>] kernel_init_freeable+0x15c/0x210
[   21.504075] [<ffffffff80619cd0>] kernel_init+0x10/0xf8
[   21.504324] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[   21.504683]
[   21.504843] rcu_sched kthread starved for 2101 jiffies!
g18446744073709551317 c18446744073709551316 f0x2 RCU_GP_WAIT_FQS(3)
->state=0x0
[   21.505320] rcu_sched       R  running task        0     7      2
0x00100000
[   21.505639] Stack : ffffffff8078e5a8 ffffffffffff00fe
000000000234fb95 0000000000000000
          0000000000000117 000000000005fcb4 00000000ffff8ae7
980000000107e600
          980000000107e600 ffffffff80780000 ffffffff80781010
ffffffff80790000
          0000000000000000 0000000000000001 0000000000000003
ffffffff8061b2b4
          0000000000000000 ffffffff8061dbac 0000000000000200
0000000000000000
          00000000ffff8ae7 ffffffff80183fa8 9800000007093000
ffffffff00000000
          0000000000000001 9800000001082f80 ffffffff8078e340
ffffffff8078e340
          ffffffff8078e5a0 ffffffff80780000 ffffffff80780000
ffffffff80181a98
          9800000007093000 9800000007097d58 9800000007097d58
0000000000000000
          0000000000000001 ffffffff80180000 ffffffff8017f140
ffffffff806e0000
          ...
[   21.508301] Call Trace:
[   21.508413] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
[   21.508668] [<ffffffff8061b2b4>] schedule+0x24/0x80
[   21.508892] [<ffffffff8061dbac>] schedule_timeout+0x11c/0x1e0
[   21.509121] [<ffffffff80181a98>] rcu_gp_kthread+0x510/0x948
[   21.509349] [<ffffffff8014a9c8>] kthread+0xc8/0xe0
[   21.509555] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[   21.509794]
^C
qemu-system-mips64el.bad: terminating on signal 2

When using '-d in_asm' I see timer interrupts are delivered and handler
executed, before the rcu_sched detects the cpu stalling.


Console output from the previous commit (330edfcc):

Linux version 4.7.0-rc1 (@859affe05464) (gcc version 6.3.0 20170516
(Debian 6.3.0-18) ) #2 SMP Sat Feb 1 18:16:17 UTC 2020
GCRs appear to have been moved (expected them at 0x1fbf8000)!
earlycon: uart8250 at I/O port 0x3f8 (options '38400n8')
bootconsole [uart8250] enabled
MIPS CPS SMP unable to proceed without a CM
CPU0 revision is: 0001a900 (MIPS I6400)
FPU revision is: 20f30300
MSA revision is: 00000300
MIPS: machine is mti,malta
Software DMA cache coherency enabled
Determined physical RAM map:
 memory: 0000000008000000 @ 0000000000000000 (usable)
Zone ranges:
  DMA      [mem 0x0000000000000000-0x0000000000ffffff]
  DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
  Normal   empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x0000000007ffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 64 bytes
percpu: Embedded 5 pages/cpu @980000000107c000 s29664 r8192 d44064 u81920
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8163
Kernel command line: clocksource=GIC console=ttyS0 printk.time=1
[    0.000000] PID hash table entries: 512 (order: -2, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 3, 131072
bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 2, 65536 bytes)
[    0.000000] Writing ErrCtl register=00000000
[    0.000000] Readback ErrCtl register=00000000
[    0.000000] MAAR configuration:
[    0.000000]   [0]: 0x0000000000010000-0x0000000007ffffff speculate
[    0.000000]   [1]: disabled
[    0.000000]   [2]: disabled
[    0.000000]   [3]: disabled
[    0.000000]   [4]: disabled
[    0.000000]   [5]: disabled
[    0.000000]   [6]: disabled
[    0.000000]   [7]: disabled
[    0.000000] Memory: 121728K/131072K available (5253K kernel code,
380K rwdata, 1276K rodata, 304K init, 278K bss, 9344K reserved, 0K
cma-reserved)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 64.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=1
[    0.000000] NR_IRQS:256
[    0.000000] CPU frequency 200.00 MHz
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112606563 ns
[    0.000227] sched_clock: 32 bits at 99MHz, resolution 10ns, wraps
every 21474838522ns
[    0.008164] Console: colour dummy device 80x25
[    0.012438] Calibrating delay loop... 910.13 BogoMIPS (lpj=4550656)
[    0.153536] pid_max: default: 32768 minimum: 301
[    0.155594] Mount-cache hash table entries: 2048 (order: 0, 16384 bytes)
[    0.156021] Mountpoint-cache hash table entries: 2048 (order: 0,
16384 bytes)
[    0.192797] Brought up 1 CPUs
[    0.203257] devtmpfs: initialized
[    0.217846] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.224678] NET: Registered protocol family 16
[    0.242230] clocksource: pit: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 1601818034827 ns
[    0.242911] pm-cps: no CM, non-coherent states unavailable
[    0.294752] vgaarb: loaded
[    0.296299] SCSI subsystem initialized
[    0.301656] PCI host bridge to bus 0000:00
[    0.302541] pci_bus 0000:00: root bus resource [mem
0x10000000-0x17ffffff]
[    0.303066] pci_bus 0000:00: root bus resource [io  0x1000-0x1fffff]
[    0.303567] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0]
[    0.304037] pci_bus 0000:00: No busn resource found for root bus,
will use [bus 00-ff]
[    0.306645] pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR
(can't size)
[    0.307287] pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR
(can't size)
[    0.307732] pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR
(can't size)
[    0.308191] pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR
(can't size)
[    0.308683] pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR
(can't size)
[    0.312906] pci 0000:00:0a.1: legacy IDE quirk: reg 0x10: [io
0x01f0-0x01f7]
[    0.313321] pci 0000:00:0a.1: legacy IDE quirk: reg 0x14: [io  0x03f6]
[    0.313834] pci 0000:00:0a.1: legacy IDE quirk: reg 0x18: [io
0x0170-0x0177]
[    0.314301] pci 0000:00:0a.1: legacy IDE quirk: reg 0x1c: [io  0x0376]
[    0.316353] pci 0000:00:0a.3: quirk: [io  0x1000-0x103f] claimed by
PIIX4 ACPI
[    0.316796] pci 0000:00:0a.3: quirk: [io  0x1100-0x110f] claimed by
PIIX4 SMB
[    0.318865] vgaarb: device added:
PCI:0000:00:12.0,decodes=io+mem,owns=none,locks=none
[    0.321353] pci 0000:00:12.0: BAR 0: assigned [mem
0x10000000-0x11ffffff pref]
[    0.322118] pci 0000:00:0b.0: BAR 6: assigned [mem
0x12000000-0x1203ffff pref]
[    0.322655] pci 0000:00:12.0: BAR 6: assigned [mem
0x12040000-0x1204ffff pref]
[    0.323124] pci 0000:00:12.0: BAR 1: assigned [mem 0x12050000-0x12050fff]
[    0.323594] pci 0000:00:0a.2: BAR 4: assigned [io  0x1040-0x105f]
[    0.323984] pci 0000:00:0b.0: BAR 0: assigned [io  0x1060-0x107f]
[    0.324368] pci 0000:00:0b.0: BAR 1: assigned [mem 0x12051000-0x1205101f]
[    0.324787] pci 0000:00:0a.1: BAR 4: assigned [io  0x1080-0x108f]
[    0.342630] clocksource: Switched to clocksource MIPS
[    0.344235] VFS: Disk quotas dquot_6.6.0
[    0.344890] VFS: Dquot-cache hash table entries: 2048 (order 0, 16384
bytes)
[    0.386512] NET: Registered protocol family 2
[    0.398836] TCP established hash table entries: 2048 (order: 0, 16384
bytes)
[    0.400383] TCP bind hash table entries: 2048 (order: 1, 32768 bytes)
[    0.400907] TCP: Hash tables configured (established 2048 bind 2048)
[    0.402979] UDP hash table entries: 512 (order: 0, 16384 bytes)
[    0.403480] UDP-Lite hash table entries: 512 (order: 0, 16384 bytes)
[    0.406146] NET: Registered protocol family 1
[    0.410131] RPC: Registered named UNIX socket transport module.
[    0.410481] RPC: Registered udp transport module.
[    0.410723] RPC: Registered tcp transport module.
[    0.410969] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.418784] futex hash table entries: 256 (order: 0, 16384 bytes)
[    0.423787] workingset: timestamp_bits=60 max_order=13 bucket_order=0
[    0.427615] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[    0.432664] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 253)
[    0.433193] io scheduler noop registered
[    0.433428] io scheduler deadline registered
[    0.433795] io scheduler cfq registered (default)
[    0.436019] PCI: Enabling device 0000:00:12.0 (0000 -> 0002)
[    0.437688] cirrusfb 0000:00:12.0: Cirrus Logic chipset on PCI bus,
RAM (4096 kB) at 0x10000000
[    0.693879] Console: switching to colour frame buffer device 80x30
[    0.890253] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.900232] console [ttyS0] disabled
[    0.931815] serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud =
115200) is a 16550A
[    0.934068] console [ttyS0] enabled
[    0.934068] console [ttyS0] enabled
[    0.934866] bootconsole [uart8250] disabled
[    0.934866] bootconsole [uart8250] disabled
[    0.963488] serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud =
115200) is a 16550A
[    0.991024] serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20,
base_baud = 230400) is a 16550A
[    0.993376] [drm] Initialized drm 1.1.0 20060810
[    1.035413] brd: module loaded
[    1.036869] PCI: Enabling device 0000:00:0a.1 (0000 -> 0001)
[    1.052237] scsi host0: ata_piix
[    1.055459] scsi host1: ata_piix
[    1.056457] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1080
irq 14
[    1.056967] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1088
irq 15
[    1.060000] physmap platform flash device: 00400000 at 1e000000
[    1.063974] physmap-flash.0: Found 1 x32 devices at 0x0 in 32-bit
bank. Manufacturer ID 0x000000 Chip ID 0x000000
[    1.065202] Intel/Sharp Extended Query Table at 0x0031
[    1.066817] Using buffer write method
[    1.080256] Creating 3 MTD partitions on "physmap-flash.0":
[    1.081618] 0x000000000000-0x000000100000 : "YAMON"
[    1.088644] 0x000000100000-0x0000003e0000 : "User FS"
[    1.091480] 0x0000003e0000-0x000000400000 : "Board Config"
[    1.094277] pcnet32: pcnet32.c:v1.35 21.Apr.2008
tsbogend@alpha.franken.de
[    1.094891] PCI: Enabling device 0000:00:0b.0 (0000 -> 0003)
[    1.096781] pcnet32: PCnet/PCI II 79C970A at 0x1060,
52:54:00:12:34:56 assigned IRQ 10
[    1.100991] pcnet32: eth0: registered as PCnet/PCI II 79C970A
[    1.101594] pcnet32: 1 cards_found
[    1.104245] mousedev: PS/2 mouse device common for all mice
[    1.107521] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
[    1.108464] rtc_cmos rtc_cmos: alarms up to one day, 242 bytes nvram
[    1.111009] NET: Registered protocol family 10
[    1.121232] sit: IPv6 over IPv4 tunneling driver
[    1.124784] NET: Registered protocol family 17
[    1.125362] NET: Registered protocol family 15
[    1.135855] rtc_cmos rtc_cmos: setting system clock to 2020-02-01
20:08:10 UTC (1580587690)
[    1.328785] ata2.00: ATAPI: QEMU DVD-ROM, 2.5+, max UDMA/100
[    1.335399] ata2.00: configured for UDMA/33
[    1.377344] scsi 1:0:0:0: CD-ROM            QEMU     QEMU DVD-ROM
 2.5+ PQ: 0 ANSI: 5
[    1.407242] sr 1:0:0:0: [sr0] scsi3-mmc drive: 4x/4x cd/rw xa/form2 tray
[    1.409546] cdrom: Uniform CD-ROM driver Revision: 3.20
...

When booting

The kernel I'm using is available here:
https://github.com/philmd/qemu-testing-blob/tree/malta_i6400/mips/malta/mips64el

It is built following the steps from:
https://www.mips.com/blog/how-to-run-smp-linux-in-qemu-on-a-mips64-release-6-cpu/
You can rebuild using docker anyway:
https://github.com/philmd/qemu-testing-blob/blob/malta_i6400/mips/malta/mips64el/Dockerfile

> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/mips/cpu.h       |   4 -
>  target/mips/op_helper.c | 182 +++++++++++++---------------------------
>  2 files changed, 60 insertions(+), 126 deletions(-)
> 
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index ca00f41daf..c218ccc4a8 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1147,10 +1147,6 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
>   * MMU modes definitions. We carefully match the indices with our
>   * hflags layout.
>   */
> -#define MMU_MODE0_SUFFIX _kernel
> -#define MMU_MODE1_SUFFIX _super
> -#define MMU_MODE2_SUFFIX _user
> -#define MMU_MODE3_SUFFIX _error
>  #define MMU_USER_IDX 2
>  
>  static inline int hflags_mmu_index(uint32_t hflags)
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 18fcee4a78..79d44da6fa 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -52,69 +52,6 @@ static void raise_exception(CPUMIPSState *env, uint32_t exception)
>      do_raise_exception(env, exception, 0);
>  }
>  
> -#if defined(CONFIG_USER_ONLY)
> -#define HELPER_LD(name, insn, type)                                     \
> -static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
> -                             int mem_idx, uintptr_t retaddr)            \
> -{                                                                       \
> -    return (type) cpu_##insn##_data_ra(env, addr, retaddr);             \
> -}
> -#else
> -#define HELPER_LD(name, insn, type)                                     \
> -static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
> -                             int mem_idx, uintptr_t retaddr)            \
> -{                                                                       \
> -    switch (mem_idx) {                                                  \
> -    case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr);   \
> -    case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr);    \
> -    default:                                                            \
> -    case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr);     \
> -    case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr);    \
> -    }                                                                   \
> -}
> -#endif
> -HELPER_LD(lw, ldl, int32_t)
> -#if defined(TARGET_MIPS64)
> -HELPER_LD(ld, ldq, int64_t)
> -#endif
> -#undef HELPER_LD
> -
> -#if defined(CONFIG_USER_ONLY)
> -#define HELPER_ST(name, insn, type)                                     \
> -static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
> -                             type val, int mem_idx, uintptr_t retaddr)  \
> -{                                                                       \
> -    cpu_##insn##_data_ra(env, addr, val, retaddr);                      \
> -}
> -#else
> -#define HELPER_ST(name, insn, type)                                     \
> -static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
> -                             type val, int mem_idx, uintptr_t retaddr)  \
> -{                                                                       \
> -    switch (mem_idx) {                                                  \
> -    case 0:                                                             \
> -        cpu_##insn##_kernel_ra(env, addr, val, retaddr);                \
> -        break;                                                          \
> -    case 1:                                                             \
> -        cpu_##insn##_super_ra(env, addr, val, retaddr);                 \
> -        break;                                                          \
> -    default:                                                            \
> -    case 2:                                                             \
> -        cpu_##insn##_user_ra(env, addr, val, retaddr);                  \
> -        break;                                                          \
> -    case 3:                                                             \
> -        cpu_##insn##_error_ra(env, addr, val, retaddr);                 \
> -        break;                                                          \
> -    }                                                                   \
> -}
> -#endif
> -HELPER_ST(sb, stb, uint8_t)
> -HELPER_ST(sw, stl, uint32_t)
> -#if defined(TARGET_MIPS64)
> -HELPER_ST(sd, stq, uint64_t)
> -#endif
> -#undef HELPER_ST
> -
>  /* 64 bits arithmetic for 32 bits hosts */
>  static inline uint64_t get_HILO(CPUMIPSState *env)
>  {
> @@ -379,12 +316,12 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
>      }                                                                         \
>      env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC());             \
>      env->lladdr = arg;                                                        \
> -    env->llval = do_##insn(env, arg, mem_idx, GETPC());                       \
> +    env->llval = cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC());          \
>      return env->llval;                                                        \
>  }
> -HELPER_LD_ATOMIC(ll, lw, 0x3)
> +HELPER_LD_ATOMIC(ll, ldl, 0x3)
>  #ifdef TARGET_MIPS64
> -HELPER_LD_ATOMIC(lld, ld, 0x7)
> +HELPER_LD_ATOMIC(lld, ldq, 0x7)
>  #endif
>  #undef HELPER_LD_ATOMIC
>  #endif
> @@ -400,42 +337,42 @@ HELPER_LD_ATOMIC(lld, ld, 0x7)
>  void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
>                  int mem_idx)
>  {
> -    do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
> +    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
>  
>      if (GET_LMASK(arg2) <= 2) {
> -        do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK(arg2) <= 1) {
> -        do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK(arg2) == 0) {
> -        do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
> +                          mem_idx, GETPC());
>      }
>  }
>  
>  void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
>                  int mem_idx)
>  {
> -    do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
> +    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
>  
>      if (GET_LMASK(arg2) >= 1) {
> -        do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK(arg2) >= 2) {
> -        do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK(arg2) == 3) {
> -        do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
> +                          mem_idx, GETPC());
>      }
>  }
>  
> @@ -453,82 +390,82 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
>  void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
>                  int mem_idx)
>  {
> -    do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
> +    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
>  
>      if (GET_LMASK64(arg2) <= 6) {
> -        do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) <= 5) {
> -        do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) <= 4) {
> -        do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) <= 3) {
> -        do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) <= 2) {
> -        do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) <= 1) {
> -        do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) <= 0) {
> -        do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
> +                          mem_idx, GETPC());
>      }
>  }
>  
>  void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
>                  int mem_idx)
>  {
> -    do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
> +    cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
>  
>      if (GET_LMASK64(arg2) >= 1) {
> -        do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) >= 2) {
> -        do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) >= 3) {
> -        do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) >= 4) {
> -        do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) >= 5) {
> -        do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) >= 6) {
> -        do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
> +                          mem_idx, GETPC());
>      }
>  
>      if (GET_LMASK64(arg2) == 7) {
> -        do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
> -              GETPC());
> +        cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
> +                          mem_idx, GETPC());
>      }
>  }
>  #endif /* TARGET_MIPS64 */
> @@ -546,14 +483,14 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
>  
>          for (i = 0; i < base_reglist; i++) {
>              env->active_tc.gpr[multiple_regs[i]] =
> -                (target_long)do_lw(env, addr, mem_idx, GETPC());
> +                (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
>              addr += 4;
>          }
>      }
>  
>      if (do_r31) {
> -        env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
> -                                                    GETPC());
> +        env->active_tc.gpr[31] =
> +            (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
>      }
>  }
>  
> @@ -567,14 +504,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
>          target_ulong i;
>  
>          for (i = 0; i < base_reglist; i++) {
> -            do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
> -                  GETPC());
> +            cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
> +                              mem_idx, GETPC());
>              addr += 4;
>          }
>      }
>  
>      if (do_r31) {
> -        do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
> +        cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
>      }
>  }
>  
> @@ -589,14 +526,15 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
>          target_ulong i;
>  
>          for (i = 0; i < base_reglist; i++) {
> -            env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
> -                                                         GETPC());
> +            env->active_tc.gpr[multiple_regs[i]] =
> +                cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
>              addr += 8;
>          }
>      }
>  
>      if (do_r31) {
> -        env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
> +        env->active_tc.gpr[31] =
> +            cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
>      }
>  }
>  
> @@ -610,14 +548,14 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
>          target_ulong i;
>  
>          for (i = 0; i < base_reglist; i++) {
> -            do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
> -                  GETPC());
> +            cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
> +                              mem_idx, GETPC());
>              addr += 8;
>          }
>      }
>  
>      if (do_r31) {
> -        do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
> +        cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
>      }
>  }
>  #endif
> 


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
  2020-02-01 20:12   ` Philippe Mathieu-Daudé
@ 2020-02-01 22:07     ` Philippe Mathieu-Daudé
  2020-02-02  2:37       ` Philippe Mathieu-Daudé
  2020-02-02  9:20     ` Thomas Huth
  1 sibling, 1 reply; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-01 22:07 UTC (permalink / raw)
  To: Richard Henderson, Alex Bennée
  Cc: peter.maydell, David Hildenbrand, qemu-devel,
	Aleksandar Markovic, Aleksandar Rikalo,
	Philippe Mathieu-Daudé,
	Aurelien Jarno

On 2/1/20 9:12 PM, Philippe Mathieu-Daudé wrote:
> Hi Richard,
> 
> On 1/8/20 4:45 AM, Richard Henderson wrote:
>> The separate suffixed functions were used to construct
>> some do_##insn function switched on mmu_idx.  The interface
>> is exactly identical to the *_mmuidx_ra functions.  Replace
>> them directly and remove the constructions.
>>
>> Cc: Aurelien Jarno <aurelien@aurel32.net>
>> Cc: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> 
> I'm seeing a regression since commit 7dd547e5a (however I'm not sure
> this particular commit introduced the regression, or instead revealed it).
> 
> I get a hang when booting a I6400 CPU on Malta:
> 
> $ qemu-system-mips64el -cpu I6400 -serial stdio \
>   -kernel vmlinux \
>   -append "clocksource=GIC console=ttyS0 printk.time=1"

FYI this binary was built using:

  ./configure --target-list=mips64el-softmmu --disable-xen
--disable-spice --disable-vnc --disable-rdma --disable-vde --disable-rbd
--disable-smartcard --disable-libusb --disable-glusterfs --disable-tpm
--disable-vhdx --disable-tools --disable-guest-agent --disable-docs
--disable-vhost-vsock --extra-cflags='-Wno-format-truncation
-Wno-stringop-truncation -Wno-address-of-packed-member'

> Linux version 4.7.0-rc1 (@859affe05464) (gcc version 6.3.0 20170516
> (Debian 6.3.0-18) ) #2 SMP Sat Feb 1 18:16:17 UTC 2020
> GCRs appear to have been moved (expected them at 0x1fbf8000)!
> earlycon: uart8250 at I/O port 0x3f8 (options '38400n8')
> bootconsole [uart8250] enabled
> MIPS CPS SMP unable to proceed without a CM
> CPU0 revision is: 0001a900 (MIPS I6400)
> FPU revision is: 20f30300
> MSA revision is: 00000300
> MIPS: machine is mti,malta
> Software DMA cache coherency enabled
> Determined physical RAM map:
>  memory: 0000000008000000 @ 0000000000000000 (usable)
> Zone ranges:
>   DMA      [mem 0x0000000000000000-0x0000000000ffffff]
>   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>   Normal   empty
> Movable zone start for each node
> Early memory node ranges
>   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
> Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
> Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
> Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 64 bytes
> percpu: Embedded 5 pages/cpu @980000000107c000 s29664 r8192 d44064 u81920
> Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8163
> Kernel command line: clocksource=GIC console=ttyS0 printk.time=1
> [    0.000000] PID hash table entries: 512 (order: -2, 4096 bytes)
> [    0.000000] Dentry cache hash table entries: 16384 (order: 3, 131072
> bytes)
> [    0.000000] Inode-cache hash table entries: 8192 (order: 2, 65536 bytes)
> [    0.000000] Writing ErrCtl register=00000000
> [    0.000000] Readback ErrCtl register=00000000
> [    0.000000] MAAR configuration:
> [    0.000000]   [0]: 0x0000000000010000-0x0000000007ffffff speculate
> [    0.000000]   [1]: disabled
> [    0.000000]   [2]: disabled
> [    0.000000]   [3]: disabled
> [    0.000000]   [4]: disabled
> [    0.000000]   [5]: disabled
> [    0.000000]   [6]: disabled
> [    0.000000]   [7]: disabled
> [    0.000000] Memory: 121728K/131072K available (5253K kernel code,
> 380K rwdata, 1276K rodata, 304K init, 278K bss, 9344K reserved, 0K
> cma-reserved)
> [    0.000000] Hierarchical RCU implementation.
> [    0.000000]  Build-time adjustment of leaf fanout to 64.
> [    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
> [    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=1
> [    0.000000] NR_IRQS:256
> [    0.000000] CPU frequency 200.00 MHz
> [    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 19112598155 ns
> [    0.000223] sched_clock: 32 bits at 100MHz, resolution 9ns, wraps
> every 21474829307ns
> [    0.008011] Console: colour dummy device 80x25
> [    0.012181] Calibrating delay loop... 950.27 BogoMIPS (lpj=4751360)
> [    0.164015] pid_max: default: 32768 minimum: 301
> [    0.165920] Mount-cache hash table entries: 2048 (order: 0, 16384 bytes)
> [    0.166244] Mountpoint-cache hash table entries: 2048 (order: 0,
> 16384 bytes)
> [    0.202498] Brought up 1 CPUs
> [    0.213199] devtmpfs: initialized
> [    0.228877] clocksource: jiffies: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 19112604462750000 ns
> [    0.236181] NET: Registered protocol family 16
> [    0.253496] clocksource: pit: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 1601818034827 ns
> [    0.254012] pm-cps: no CM, non-coherent states unavailable
> [    0.257508] ------------[ cut here ]------------
> [    0.258085] WARNING: CPU: 0 PID: 1 at fs/kernfs/dir.c:502
> __kernfs_remove+0x250/0x258
> [    0.258489] Modules linked in:
> [   21.494186] INFO: rcu_sched detected stalls on CPUs/tasks:
> [   21.494530]  (detected by 0, t=2102 jiffies, g=-299, c=-300, q=1)
> [   21.494921] All QSes seen, last rcu_sched kthread activity 2101
> (4294939419-4294937318), jiffies_till_next_fqs=1, root ->qsmask 0x0
> [   21.495583] swapper/0       R  running task        0     1      0
> 0x00100004
> [   21.496028] Stack : 000000000000001d 0000000000000004
> ffffffff80790000 ffffffff80820000
>           0000000000000000 0000000000000000 000000000000001d
> 0000000000000002
>           ffffffff80820000 ffffffff80170c70 0000000000000000
> 0000000000000000
>           0000000000000000 ffffffff80822328 0000000000000001
> ffffffff80822328
>           9800000007052fc0 ffffffff80780000 ffffffff8078e340
> ffffffff8078e340
>           ffffffff80780000 ffffffff80780000 ffffffff80781010
> ffffffff8078e540
>           0000000000000000 0000000000000000 0000000000000000
> 0000000000000000
>           0000000000000000 98000000070577b0 0000000000000000
> ffffffff80182a64
>           0000000000000000 0000000000000000 0000000000100004
> 9800000007052fc0
>           ffffffff80780000 ffffffff8010c460 9800000001082f80
> ffffffff80182a64
>           ...
> [   21.498954] Call Trace:
> [   21.499132] [<ffffffff8010c460>] show_stack+0x80/0xa0
> [   21.499520] [<ffffffff80182a64>] rcu_check_callbacks+0x804/0x810
> [   21.499744] [<ffffffff80185360>] update_process_times+0x38/0x70
> [   21.499981] [<ffffffff80193c34>] tick_handle_periodic+0x2c/0xa8
> [   21.500215] [<ffffffff801114b4>] c0_compare_interrupt+0x74/0xb8
> [   21.500451] [<ffffffff80172e18>] handle_irq_event_percpu+0x80/0x1a0
> [   21.500707] [<ffffffff801775ac>] handle_percpu_irq+0x7c/0xb8
> [   21.500935] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
> [   21.501176] [<ffffffff80108010>] do_IRQ+0x18/0x28
> [   21.501369] [<ffffffff803746c4>] plat_irq_dispatch+0x64/0xa0
> [   21.501606] [<ffffffff80106370>] ret_from_irq+0x0/0x4
> [   21.501868] [<ffffffff8034573c>] dump_stack+0x6c/0xd0
> [   21.502068] [<ffffffff8012d088>] __warn+0xf0/0x108
> [   21.502268] [<ffffffff80269e78>] __kernfs_remove+0x250/0x258
> [   21.502519] [<ffffffff8026ae38>] kernfs_remove_by_name_ns+0x48/0xb0
> [   21.502771] [<ffffffff8026dc44>] remove_files.isra.0+0x44/0x98
> [   21.503003] [<ffffffff8026e034>] sysfs_remove_group+0x4c/0xc0
> [   21.503339] [<ffffffff807cbc18>] param_sysfs_init+0x178/0x1f0
> [   21.503605] [<ffffffff80100564>] do_one_initcall+0x3c/0x148
> [   21.503830] [<ffffffff807c4b38>] kernel_init_freeable+0x15c/0x210
> [   21.504075] [<ffffffff80619cd0>] kernel_init+0x10/0xf8
> [   21.504324] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
> [   21.504683]
> [   21.504843] rcu_sched kthread starved for 2101 jiffies!
> g18446744073709551317 c18446744073709551316 f0x2 RCU_GP_WAIT_FQS(3)
> ->state=0x0
> [   21.505320] rcu_sched       R  running task        0     7      2
> 0x00100000
> [   21.505639] Stack : ffffffff8078e5a8 ffffffffffff00fe
> 000000000234fb95 0000000000000000
>           0000000000000117 000000000005fcb4 00000000ffff8ae7
> 980000000107e600
>           980000000107e600 ffffffff80780000 ffffffff80781010
> ffffffff80790000
>           0000000000000000 0000000000000001 0000000000000003
> ffffffff8061b2b4
>           0000000000000000 ffffffff8061dbac 0000000000000200
> 0000000000000000
>           00000000ffff8ae7 ffffffff80183fa8 9800000007093000
> ffffffff00000000
>           0000000000000001 9800000001082f80 ffffffff8078e340
> ffffffff8078e340
>           ffffffff8078e5a0 ffffffff80780000 ffffffff80780000
> ffffffff80181a98
>           9800000007093000 9800000007097d58 9800000007097d58
> 0000000000000000
>           0000000000000001 ffffffff80180000 ffffffff8017f140
> ffffffff806e0000
>           ...
> [   21.508301] Call Trace:
> [   21.508413] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
> [   21.508668] [<ffffffff8061b2b4>] schedule+0x24/0x80
> [   21.508892] [<ffffffff8061dbac>] schedule_timeout+0x11c/0x1e0
> [   21.509121] [<ffffffff80181a98>] rcu_gp_kthread+0x510/0x948
> [   21.509349] [<ffffffff8014a9c8>] kthread+0xc8/0xe0
> [   21.509555] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
> [   21.509794]
> ^C
> qemu-system-mips64el.bad: terminating on signal 2
> 
> When using '-d in_asm' I see timer interrupts are delivered and handler
> executed, before the rcu_sched detects the cpu stalling.
> 
> 
> Console output from the previous commit (330edfcc):
> 
> Linux version 4.7.0-rc1 (@859affe05464) (gcc version 6.3.0 20170516
> (Debian 6.3.0-18) ) #2 SMP Sat Feb 1 18:16:17 UTC 2020
> GCRs appear to have been moved (expected them at 0x1fbf8000)!
> earlycon: uart8250 at I/O port 0x3f8 (options '38400n8')
> bootconsole [uart8250] enabled
> MIPS CPS SMP unable to proceed without a CM
> CPU0 revision is: 0001a900 (MIPS I6400)
> FPU revision is: 20f30300
> MSA revision is: 00000300
> MIPS: machine is mti,malta
> Software DMA cache coherency enabled
> Determined physical RAM map:
>  memory: 0000000008000000 @ 0000000000000000 (usable)
> Zone ranges:
>   DMA      [mem 0x0000000000000000-0x0000000000ffffff]
>   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>   Normal   empty
> Movable zone start for each node
> Early memory node ranges
>   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
> Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
> Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
> Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 64 bytes
> percpu: Embedded 5 pages/cpu @980000000107c000 s29664 r8192 d44064 u81920
> Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8163
> Kernel command line: clocksource=GIC console=ttyS0 printk.time=1
> [    0.000000] PID hash table entries: 512 (order: -2, 4096 bytes)
> [    0.000000] Dentry cache hash table entries: 16384 (order: 3, 131072
> bytes)
> [    0.000000] Inode-cache hash table entries: 8192 (order: 2, 65536 bytes)
> [    0.000000] Writing ErrCtl register=00000000
> [    0.000000] Readback ErrCtl register=00000000
> [    0.000000] MAAR configuration:
> [    0.000000]   [0]: 0x0000000000010000-0x0000000007ffffff speculate
> [    0.000000]   [1]: disabled
> [    0.000000]   [2]: disabled
> [    0.000000]   [3]: disabled
> [    0.000000]   [4]: disabled
> [    0.000000]   [5]: disabled
> [    0.000000]   [6]: disabled
> [    0.000000]   [7]: disabled
> [    0.000000] Memory: 121728K/131072K available (5253K kernel code,
> 380K rwdata, 1276K rodata, 304K init, 278K bss, 9344K reserved, 0K
> cma-reserved)
> [    0.000000] Hierarchical RCU implementation.
> [    0.000000]  Build-time adjustment of leaf fanout to 64.
> [    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
> [    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=1
> [    0.000000] NR_IRQS:256
> [    0.000000] CPU frequency 200.00 MHz
> [    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 19112606563 ns
> [    0.000227] sched_clock: 32 bits at 99MHz, resolution 10ns, wraps
> every 21474838522ns
> [    0.008164] Console: colour dummy device 80x25
> [    0.012438] Calibrating delay loop... 910.13 BogoMIPS (lpj=4550656)
> [    0.153536] pid_max: default: 32768 minimum: 301
> [    0.155594] Mount-cache hash table entries: 2048 (order: 0, 16384 bytes)
> [    0.156021] Mountpoint-cache hash table entries: 2048 (order: 0,
> 16384 bytes)
> [    0.192797] Brought up 1 CPUs
> [    0.203257] devtmpfs: initialized
> [    0.217846] clocksource: jiffies: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 19112604462750000 ns
> [    0.224678] NET: Registered protocol family 16
> [    0.242230] clocksource: pit: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 1601818034827 ns
> [    0.242911] pm-cps: no CM, non-coherent states unavailable
> [    0.294752] vgaarb: loaded
> [    0.296299] SCSI subsystem initialized
> [    0.301656] PCI host bridge to bus 0000:00
> [    0.302541] pci_bus 0000:00: root bus resource [mem
> 0x10000000-0x17ffffff]
> [    0.303066] pci_bus 0000:00: root bus resource [io  0x1000-0x1fffff]
> [    0.303567] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0]
> [    0.304037] pci_bus 0000:00: No busn resource found for root bus,
> will use [bus 00-ff]
> [    0.306645] pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR
> (can't size)
> [    0.307287] pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR
> (can't size)
> [    0.307732] pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR
> (can't size)
> [    0.308191] pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR
> (can't size)
> [    0.308683] pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR
> (can't size)
> [    0.312906] pci 0000:00:0a.1: legacy IDE quirk: reg 0x10: [io
> 0x01f0-0x01f7]
> [    0.313321] pci 0000:00:0a.1: legacy IDE quirk: reg 0x14: [io  0x03f6]
> [    0.313834] pci 0000:00:0a.1: legacy IDE quirk: reg 0x18: [io
> 0x0170-0x0177]
> [    0.314301] pci 0000:00:0a.1: legacy IDE quirk: reg 0x1c: [io  0x0376]
> [    0.316353] pci 0000:00:0a.3: quirk: [io  0x1000-0x103f] claimed by
> PIIX4 ACPI
> [    0.316796] pci 0000:00:0a.3: quirk: [io  0x1100-0x110f] claimed by
> PIIX4 SMB
> [    0.318865] vgaarb: device added:
> PCI:0000:00:12.0,decodes=io+mem,owns=none,locks=none
> [    0.321353] pci 0000:00:12.0: BAR 0: assigned [mem
> 0x10000000-0x11ffffff pref]
> [    0.322118] pci 0000:00:0b.0: BAR 6: assigned [mem
> 0x12000000-0x1203ffff pref]
> [    0.322655] pci 0000:00:12.0: BAR 6: assigned [mem
> 0x12040000-0x1204ffff pref]
> [    0.323124] pci 0000:00:12.0: BAR 1: assigned [mem 0x12050000-0x12050fff]
> [    0.323594] pci 0000:00:0a.2: BAR 4: assigned [io  0x1040-0x105f]
> [    0.323984] pci 0000:00:0b.0: BAR 0: assigned [io  0x1060-0x107f]
> [    0.324368] pci 0000:00:0b.0: BAR 1: assigned [mem 0x12051000-0x1205101f]
> [    0.324787] pci 0000:00:0a.1: BAR 4: assigned [io  0x1080-0x108f]
> [    0.342630] clocksource: Switched to clocksource MIPS
> [    0.344235] VFS: Disk quotas dquot_6.6.0
> [    0.344890] VFS: Dquot-cache hash table entries: 2048 (order 0, 16384
> bytes)
> [    0.386512] NET: Registered protocol family 2
> [    0.398836] TCP established hash table entries: 2048 (order: 0, 16384
> bytes)
> [    0.400383] TCP bind hash table entries: 2048 (order: 1, 32768 bytes)
> [    0.400907] TCP: Hash tables configured (established 2048 bind 2048)
> [    0.402979] UDP hash table entries: 512 (order: 0, 16384 bytes)
> [    0.403480] UDP-Lite hash table entries: 512 (order: 0, 16384 bytes)
> [    0.406146] NET: Registered protocol family 1
> [    0.410131] RPC: Registered named UNIX socket transport module.
> [    0.410481] RPC: Registered udp transport module.
> [    0.410723] RPC: Registered tcp transport module.
> [    0.410969] RPC: Registered tcp NFSv4.1 backchannel transport module.
> [    0.418784] futex hash table entries: 256 (order: 0, 16384 bytes)
> [    0.423787] workingset: timestamp_bits=60 max_order=13 bucket_order=0
> [    0.427615] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
> [    0.432664] Block layer SCSI generic (bsg) driver version 0.4 loaded
> (major 253)
> [    0.433193] io scheduler noop registered
> [    0.433428] io scheduler deadline registered
> [    0.433795] io scheduler cfq registered (default)
> [    0.436019] PCI: Enabling device 0000:00:12.0 (0000 -> 0002)
> [    0.437688] cirrusfb 0000:00:12.0: Cirrus Logic chipset on PCI bus,
> RAM (4096 kB) at 0x10000000
> [    0.693879] Console: switching to colour frame buffer device 80x30
> [    0.890253] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
> [    0.900232] console [ttyS0] disabled
> [    0.931815] serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud =
> 115200) is a 16550A
> [    0.934068] console [ttyS0] enabled
> [    0.934068] console [ttyS0] enabled
> [    0.934866] bootconsole [uart8250] disabled
> [    0.934866] bootconsole [uart8250] disabled
> [    0.963488] serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud =
> 115200) is a 16550A
> [    0.991024] serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20,
> base_baud = 230400) is a 16550A
> [    0.993376] [drm] Initialized drm 1.1.0 20060810
> [    1.035413] brd: module loaded
> [    1.036869] PCI: Enabling device 0000:00:0a.1 (0000 -> 0001)
> [    1.052237] scsi host0: ata_piix
> [    1.055459] scsi host1: ata_piix
> [    1.056457] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1080
> irq 14
> [    1.056967] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1088
> irq 15
> [    1.060000] physmap platform flash device: 00400000 at 1e000000
> [    1.063974] physmap-flash.0: Found 1 x32 devices at 0x0 in 32-bit
> bank. Manufacturer ID 0x000000 Chip ID 0x000000
> [    1.065202] Intel/Sharp Extended Query Table at 0x0031
> [    1.066817] Using buffer write method
> [    1.080256] Creating 3 MTD partitions on "physmap-flash.0":
> [    1.081618] 0x000000000000-0x000000100000 : "YAMON"
> [    1.088644] 0x000000100000-0x0000003e0000 : "User FS"
> [    1.091480] 0x0000003e0000-0x000000400000 : "Board Config"
> [    1.094277] pcnet32: pcnet32.c:v1.35 21.Apr.2008
> tsbogend@alpha.franken.de
> [    1.094891] PCI: Enabling device 0000:00:0b.0 (0000 -> 0003)
> [    1.096781] pcnet32: PCnet/PCI II 79C970A at 0x1060,
> 52:54:00:12:34:56 assigned IRQ 10
> [    1.100991] pcnet32: eth0: registered as PCnet/PCI II 79C970A
> [    1.101594] pcnet32: 1 cards_found
> [    1.104245] mousedev: PS/2 mouse device common for all mice
> [    1.107521] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
> [    1.108464] rtc_cmos rtc_cmos: alarms up to one day, 242 bytes nvram
> [    1.111009] NET: Registered protocol family 10
> [    1.121232] sit: IPv6 over IPv4 tunneling driver
> [    1.124784] NET: Registered protocol family 17
> [    1.125362] NET: Registered protocol family 15
> [    1.135855] rtc_cmos rtc_cmos: setting system clock to 2020-02-01
> 20:08:10 UTC (1580587690)
> [    1.328785] ata2.00: ATAPI: QEMU DVD-ROM, 2.5+, max UDMA/100
> [    1.335399] ata2.00: configured for UDMA/33
> [    1.377344] scsi 1:0:0:0: CD-ROM            QEMU     QEMU DVD-ROM
>  2.5+ PQ: 0 ANSI: 5
> [    1.407242] sr 1:0:0:0: [sr0] scsi3-mmc drive: 4x/4x cd/rw xa/form2 tray
> [    1.409546] cdrom: Uniform CD-ROM driver Revision: 3.20
> ...
> 
> When booting
> 
> The kernel I'm using is available here:
> https://github.com/philmd/qemu-testing-blob/tree/malta_i6400/mips/malta/mips64el
> 
> It is built following the steps from:
> https://www.mips.com/blog/how-to-run-smp-linux-in-qemu-on-a-mips64-release-6-cpu/
> You can rebuild using docker anyway:
> https://github.com/philmd/qemu-testing-blob/blob/malta_i6400/mips/malta/mips64el/Dockerfile

I'm not sure this is not related to this commit, but it certainly
changes something.

I can reproduce 1/10 on commit 330edfcc84 building with --enable-debug,
while 10/10 using commit 7dd547e5a.


Console log using --enable-debug on 330edfcc84:

Linux version 4.7.0-rc1 (@859affe05464) (gcc version 6.3.0 20170516
(Debian 6.3.0-18) ) #2 SMP Sat Feb 1 18:16:17 UTC 2020
earlycon: uart8250 at I/O port 0x3f8 (options '38400n8')
bootconsole [uart8250] enabled
CPU0 revision is: 0001a900 (MIPS I6400)
FPU revision is: 20f30300
MSA revision is: 00000300
MIPS: machine is mti,malta
Software DMA cache coherency enabled
Determined physical RAM map:
 memory: 0000000008000000 @ 0000000000000000 (usable)
Zone ranges:
  DMA      [mem 0x0000000000000000-0x0000000000ffffff]
  DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
  Normal   empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x0000000007ffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
VP topology {8} total 8
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 64 bytes
percpu: Embedded 5 pages/cpu @980000000107c000 s29664 r8192 d44064 u81920
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8163
Kernel command line: clocksource=GIC console=ttyS0 printk.time=1
[    0.000000] log_buf_len individual max cpu contribution: 4096 bytes
[    0.000000] log_buf_len total cpu_extra contributions: 28672 bytes
[    0.000000] log_buf_len min size: 32768 bytes
[    0.000000] log_buf_len: 65536 bytes
[    0.000000] early log buf free: 30424(92%)
[    0.000000] PID hash table entries: 512 (order: -2, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 3, 131072
bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 2, 65536 bytes)
[    0.000000] Writing ErrCtl register=00000000
[    0.000000] Readback ErrCtl register=00000000
[    0.000000] MAAR configuration:
[    0.000000]   [0]: 0x0000000000010000-0x0000000007ffffff speculate
[    0.000000]   [1]: disabled
[    0.000000]   [2]: disabled
[    0.000000]   [3]: disabled
[    0.000000]   [4]: disabled
[    0.000000]   [5]: disabled
[    0.000000]   [6]: disabled
[    0.000000]   [7]: disabled
[    0.000000] Memory: 121104K/131072K available (5253K kernel code,
380K rwdata, 1276K rodata, 304K init, 278K bss, 9968K reserved, 0K
cma-reserved)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 64.
[    0.000000] NR_IRQS:256
[    0.000000] CPU frequency 200.00 MHz
[    0.000000] GIC frequency 99.98 MHz
[    0.000000] clocksource: GIC: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19117033123 ns
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112620523 ns
[    0.000787] sched_clock: 32 bits at 99MHz, resolution 10ns, wraps
every 21474854906ns
[    0.045704] Console: colour dummy device 80x25
[    0.053021] Calibrating delay loop... 1325.46 BogoMIPS (lpj=6627328)
[    0.129932] pid_max: default: 32768 minimum: 301
[    0.136234] Mount-cache hash table entries: 2048 (order: 0, 16384 bytes)
[    0.136906] Mountpoint-cache hash table entries: 2048 (order: 0,
16384 bytes)
[   41.031274] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.033583] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.054201] CPU1 revision is: 0001a900 (MIPS I6400)
[   41.055728] FPU revision is: 20f30300
[   41.055863] MSA revision is: 00000300
[    0.442532] Synchronize counters for CPU 1: done.
[   41.014309] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.014327] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.014786] CPU2 revision is: 0001a900 (MIPS I6400)
[   41.014798] FPU revision is: 20f30300
[   41.014804] MSA revision is: 00000300
[    0.504208] Synchronize counters for CPU 2: done.
[   41.014212] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.014229] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.014579] CPU3 revision is: 0001a900 (MIPS I6400)
[   41.014592] FPU revision is: 20f30300
[   41.014599] MSA revision is: 00000300
[    0.544586] Synchronize counters for CPU 3: done.
[   41.014251] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.014272] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.014563] CPU4 revision is: 0001a900 (MIPS I6400)
[   41.014576] FPU revision is: 20f30300
[   41.014582] MSA revision is: 00000300
[    0.695674] Synchronize counters for CPU 4: done.
[   41.014280] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.014309] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.014659] CPU5 revision is: 0001a900 (MIPS I6400)
[   41.014675] FPU revision is: 20f30300
[   41.014684] MSA revision is: 00000300
[    0.929436] Synchronize counters for CPU 5: done.
[   41.014251] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.014271] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.014600] CPU6 revision is: 0001a900 (MIPS I6400)
[   41.014612] FPU revision is: 20f30300
[   41.014618] MSA revision is: 00000300
[    0.969928] Synchronize counters for CPU 6: done.
[   41.014292] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.014313] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.014625] CPU7 revision is: 0001a900 (MIPS I6400)
[   41.014638] FPU revision is: 20f30300
[   41.014644] MSA revision is: 00000300
[    1.051137] Synchronize counters for CPU 7: done.
[    1.051764] Brought up 8 CPUs
[    1.121113] devtmpfs: initialized
[    1.215360] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462750000 ns
[    1.358645] NET: Registered protocol family 16
[    1.392339] pm-cps: CPC does not support clock gating
[    1.732391] vgaarb: loaded
[    1.811916] SCSI subsystem initialized
[    1.829400] PCI host bridge to bus 0000:00
[    1.833354] pci_bus 0000:00: root bus resource [mem
0x10000000-0x17ffffff]
[    1.834048] pci_bus 0000:00: root bus resource [io  0x1000-0x1fffff]
[    1.834760] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0]
[    1.835537] pci_bus 0000:00: No busn resource found for root bus,
will use [bus 00-ff]
[    1.845795] pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR
(can't size)
[    1.846928] pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR
(can't size)
[    1.847531] pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR
(can't size)
[    1.848025] pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR
(can't size)
[    1.848970] pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR
(can't size)
[    1.874551] pci 0000:00:0a.1: legacy IDE quirk: reg 0x10: [io
0x01f0-0x01f7]
[    1.875292] pci 0000:00:0a.1: legacy IDE quirk: reg 0x14: [io  0x03f6]
[    1.876094] pci 0000:00:0a.1: legacy IDE quirk: reg 0x18: [io
0x0170-0x0177]
[    1.876873] pci 0000:00:0a.1: legacy IDE quirk: reg 0x1c: [io  0x0376]
[    1.884188] pci 0000:00:0a.3: quirk: [io  0x1000-0x103f] claimed by
PIIX4 ACPI
[    1.884928] pci 0000:00:0a.3: quirk: [io  0x1100-0x110f] claimed by
PIIX4 SMB
[    1.890092] vgaarb: device added:
PCI:0000:00:12.0,decodes=io+mem,owns=none,locks=none
[    1.900721] pci 0000:00:12.0: BAR 0: assigned [mem
0x10000000-0x10ffffff pref]
[    1.902774] pci 0000:00:0b.0: BAR 6: assigned [mem
0x11000000-0x1103ffff pref]
[    1.903875] pci 0000:00:12.0: BAR 6: assigned [mem
0x11040000-0x1104ffff pref]
[    1.904908] pci 0000:00:13.0: BAR 4: assigned [mem
0x11050000-0x11053fff 64bit pref]
[    1.906044] pci 0000:00:12.0: BAR 2: assigned [mem 0x11054000-0x11054fff]
[    1.906570] pci 0000:00:0a.2: BAR 4: assigned [io  0x1040-0x105f]
[    1.906963] pci 0000:00:0b.0: BAR 0: assigned [io  0x1060-0x107f]
[    1.907308] pci 0000:00:0b.0: BAR 1: assigned [mem 0x11055000-0x1105501f]
[    1.908194] pci 0000:00:0a.1: BAR 4: assigned [io  0x1080-0x108f]
[    1.967033] clocksource: Switched to clocksource GIC
[   22.982466] INFO: rcu_sched detected stalls on CPUs/tasks:
[   22.998174]  2-...: (1 GPs behind) idle=37e/0/0 softirq=55/57 fqs=1
[   23.002730]  (detected by 3, t=2104 jiffies, g=-272, c=-273, q=128)
[   23.007730] Task dump for CPU 2:
[   23.010438] swapper/2       R  running task        0     0      1
0x00100000
[   23.013820] Stack : ffffffff806dd460 ffffffff807c0000
0000000000000001 ffffffff80780e78
          ffffffff807807c0 0000000000000001 00000000001abff1
ffffffff80107f18
          ffffffff806dd460 ffffffff807c0000 98000000070c8000
98000000070cbdf0
          ffffffff80780000 ffffffff80166758 000000001400fce3
ffffffff80780e78
          ffffffff807807c0 ffffffff80195630 0000000000800400
ffffffff80166754
          000000000000000a ffffffff8012eec8 ffffffff807805c0
0000000000000001
          0000000000000008 0000000000000008 ffffffff8081cc40
ffffffff80114914
          0000000000000001 0000000000000000 0000000000000004
0000000000000002
          ffffffff80820000 0000000000000000 0000000000000005
0000000000000000
          0000000000000000 0000000000000000 0000000000000000
0000000000000000
          ...
[   23.022834] Call Trace:
[   23.025982] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
[   23.029166]
[   23.031304] rcu_sched kthread starved for 2106 jiffies!
g18446744073709551344 c18446744073709551343 f0x0 RCU_GP_WAIT_FQS(3)
->state=0x1
[   23.033442] rcu_sched       S ffffffff8061b2b4     0     7      2
0x00100000
[   23.034900] Stack : 00000000000001d7 ffffffff8078e340
00000000ffff8b7d 0000000000000005
          98000000070afce0 980000000110a600 00000000ffff8b8d
980000000110a600
          980000000110a600 ffffffff80780000 ffffffff80781010
ffffffff80790000
          0000000000000000 0000000000000001 0000000000000003
ffffffff8061b2b4
          ffffffff80790000 ffffffff8061dbac 0000000000000000
980000000110aaa0
          00000000ffff8b8d ffffffff80183fa8 98000000070ab000
ffffffff00000007
          0000000000000001 ffffffff80780000 ffffffff8078e340
ffffffff8078e340
          ffffffff8078e5a0 ffffffff80780000 ffffffff80780000
ffffffff80181a98
          98000000070ab000 ffffffff8078e5a8 ffffffff8078e5a8
0000000000000000
          0000000000000000 ffffffff80180000 ffffffff8017f140
ffffffff806e0000
          ...
[   23.042338] Call Trace:
[   23.042732] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
[   23.043187] [<ffffffff8061b2b4>] schedule+0x24/0x80
[   23.043567] [<ffffffff8061dbac>] schedule_timeout+0x11c/0x1e0
[   23.043943] [<ffffffff80181a98>] rcu_gp_kthread+0x510/0x948
[   23.044381] [<ffffffff8014a9c8>] kthread+0xc8/0xe0
[   23.044702] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[   23.045165]
[   44.055135] INFO: rcu_sched detected stalls on CPUs/tasks:
[   44.058011]  7-...: (0 ticks this GP) idle=232/0/0 softirq=45/45 fqs=1
[   44.059496]  (detected by 0, t=2102 jiffies, g=-271, c=-272, q=88)
[   44.061806] Task dump for CPU 7:
[   44.063035] swapper/7       R  running task        0     0      1
0x00100000
[   44.067350] Stack : ffffffff806dd460 ffffffff807c0000
0000000000000001 980000000110ba08
          0000000000000007 ffffffff806dd460 ffffffff807c0000
ffffffff80195080
          7fffffffffffffff ffffffff807c0000 ffffffff80780000
ffffffff80780e78
          ffffffff806dd460 ffffffff807c0000 0000000000000001
ffffffff80780e78
          ffffffff80780cc0 ffffffff80195630 ffffffff806dd460
ffffffff80166754
          000000000000000a ffffffff8012eec8 ffffffff807805c0
0000000000000001
          0000000000000008 0000000000000008 ffffffff8081cc40
ffffffff80114914
          0000000000000001 0000000000000000 0000000000000080
0000000000000007
          ffffffff80820000 0000000000000000 0000000000000005
0000000000000000
          0000000000000000 0000000000000000 0000000000000000
0000000000000000
          ...
[   44.078926] Call Trace:
[   44.079358] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
[   44.079998]
[   44.080211] rcu_sched kthread starved for 2101 jiffies!
g18446744073709551345 c18446744073709551344 f0x0 RCU_GP_WAIT_FQS(3)
->state=0x1
[   44.081905] rcu_sched       S ffffffff8061b2b4     0     7      2
0x00100000
[   44.082736] Stack : 00000000000001d7 ffffffff8078e340
00000000ffff8b7d 0000000000000005
          98000000070afce0 980000000110a600 00000000ffff93c9
980000000110a600
          980000000110a600 ffffffff80780000 ffffffff80781010
ffffffff80790000
          0000000000000000 0000000000000001 0000000000000003
ffffffff8061b2b4
          ffffffff80790000 ffffffff8061dbac 0000000000000000
980000000110aed0
          00000000ffff93c9 ffffffff80183fa8 98000000070ab000
ffffffff00000007
          0000000000000001 ffffffff80780000 ffffffff8078e340
ffffffff8078e340
          ffffffff8078e5a0 ffffffff80780000 ffffffff80780000
ffffffff80181a98
          98000000070ab000 ffffffff8078e5a8 ffffffff8078e5a8
0000000000000000
          0000000000000000 ffffffff80180000 ffffffff8017f140
ffffffff806e0000
          ...
[   44.089552] Call Trace:
[   44.089733] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
[   44.090069] [<ffffffff8061b2b4>] schedule+0x24/0x80
[   44.090375] [<ffffffff8061dbac>] schedule_timeout+0x11c/0x1e0
[   44.090743] [<ffffffff80181a98>] rcu_gp_kthread+0x510/0x948
[   44.091093] [<ffffffff8014a9c8>] kthread+0xc8/0xe0
[   44.091395] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[   44.091767]
[   44.945325] VFS: Disk quotas dquot_6.6.0
[   44.984731] VFS: Dquot-cache hash table entries: 2048 (order 0, 16384
bytes)
[   45.176126] NET: Registered protocol family 2
[   45.414925] TCP established hash table entries: 2048 (order: 0, 16384
bytes)
[   45.419093] TCP bind hash table entries: 2048 (order: 1, 32768 bytes)
[   45.421411] TCP: Hash tables configured (established 2048 bind 2048)
[   45.430481] UDP hash table entries: 512 (order: 0, 16384 bytes)
[   45.431498] UDP-Lite hash table entries: 512 (order: 0, 16384 bytes)
[   45.534362] NET: Registered protocol family 1
[   45.606926] RPC: Registered named UNIX socket transport module.
[   45.608354] RPC: Registered udp transport module.
[   45.609336] RPC: Registered tcp transport module.
[   45.610249] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   45.718310] futex hash table entries: 2048 (order: 3, 131072 bytes)
[   45.747210] workingset: timestamp_bits=60 max_order=13 bucket_order=0
[   46.275627] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[   46.354259] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 253)
[   46.355680] io scheduler noop registered
[   46.356208] io scheduler deadline registered
[   46.395936] io scheduler cfq registered (default)
[   46.512436] PCI: Enabling device 0000:00:13.0 (0000 -> 0002)
[   46.555822] input: QEMU Virtio Keyboard as
/devices/pci0000:00/0000:00:13.0/virtio0/input/input0
[   46.716413] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[   46.756069] console [ttyS0] disabled
[   46.787920] serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud =
115200) is a 16550A
[   46.795739] console [ttyS0] enabled
[   46.795739] console [ttyS0] enabled
[   46.797338] bootconsole [uart8250] disabled
[   46.797338] bootconsole [uart8250] disabled
[   46.818839] serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud =
115200) is a 16550A
[   46.839273] serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20,
base_baud = 230400) is a 16550A
[   46.842492] [drm] Initialized drm 1.1.0 20060810
[   46.854005] PCI: Enabling device 0000:00:12.0 (0000 -> 0002)
[   46.859898] [drm] Found bochs VGA, ID 0xb0c5.
[   46.860297] [drm] Framebuffer size 16384 kB @ 0x10000000, mmio @
0x11054000.
[   46.866727] [TTM] Zone  kernel: Available graphics memory: 60552 kiB
[   46.867364] [TTM] Initializing pool allocator
[   47.092723] Console: switching to colour frame buffer device 128x48
[   47.117712] bochs-drm 0000:00:12.0: fb0: bochsdrmfb frame buffer device
[   47.121833] [drm] Initialized bochs-drm 1.0.0 20130925 for
0000:00:12.0 on minor 0
[   47.307909] brd: module loaded
[   47.325590] PCI: Enabling device 0000:00:0a.1 (0000 -> 0001)
[   47.379430] scsi host0: ata_piix
[   47.391937] scsi host1: ata_piix
[   47.394914] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1080
irq 14
[   47.395537] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1088
irq 15
[   47.407079] physmap platform flash device: 00400000 at 1e000000
[   47.420227] physmap-flash.0: Found 1 x32 devices at 0x0 in 32-bit
bank. Manufacturer ID 0x000000 Chip ID 0x000000
[   47.424040] Intel/Sharp Extended Query Table at 0x0031
[   47.427841] Using buffer write method
[   47.441991] Creating 3 MTD partitions on "physmap-flash.0":
[   47.445025] 0x000000000000-0x000000100000 : "YAMON"
[   47.459268] 0x000000100000-0x0000003e0000 : "User FS"
[   47.463336] 0x0000003e0000-0x000000400000 : "Board Config"
[   47.469471] pcnet32: pcnet32.c:v1.35 21.Apr.2008
tsbogend@alpha.franken.de
[   47.470336] PCI: Enabling device 0000:00:0b.0 (0000 -> 0003)
[   47.477538] pcnet32: PCnet/PCI II 79C970A at 0x1060,
52:54:00:12:34:56 assigned IRQ 10
[   47.515743] pcnet32: eth0: registered as PCnet/PCI II 79C970A
[   47.516844] pcnet32: 1 cards_found
[   47.526661] mousedev: PS/2 mouse device common for all mice
[   47.539046] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0
[   47.541127] rtc_cmos rtc_cmos: alarms up to one day, 242 bytes nvram
[   47.643909] ata2.00: ATAPI: QEMU DVD-ROM, 2.5+, max UDMA/100
[   47.651047] ata2.00: configured for UDMA/33
[   47.704763] scsi 1:0:0:0: CD-ROM            QEMU     QEMU DVD-ROM
 2.5+ PQ: 0 ANSI: 5
[   47.830833] sr 1:0:0:0: [sr0] scsi3-mmc drive: 4x/4x cd/rw xa/form2 tray
[   47.833285] cdrom: Uniform CD-ROM driver Revision: 3.20
[   47.855442] NET: Registered protocol family 10
[   48.049944] sit: IPv6 over IPv4 tunneling driver
[   48.135772] NET: Registered protocol family 17
[   48.137211] NET: Registered protocol family 15
[   48.188261] rtc_cmos rtc_cmos: setting system clock to 2020-02-01
21:54:13 UTC (1580594053)

While there is no activity during 20s after "clocksource: Switched to
clocksource GIC" is displayed, QEMU use very little resources (3% on a
core).


Console log using --enable-debug on 7dd547e5a:

Linux version 4.7.0-rc1 (@859affe05464) (gcc version 6.3.0 20170516
(Debian 6.3.0-18) ) #2 SMP Sat Feb 1 18:16:17 UTC 2020
earlycon: uart8250 at I/O port 0x3f8 (options '38400n8')
bootconsole [uart8250] enabled
CPU0 revision is: 0001a900 (MIPS I6400)
FPU revision is: 20f30300
MSA revision is: 00000300
MIPS: machine is mti,malta
Software DMA cache coherency enabled
Determined physical RAM map:
 memory: 0000000008000000 @ 0000000000000000 (usable)
Zone ranges:
  DMA      [mem 0x0000000000000000-0x0000000000ffffff]
  DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
  Normal   empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x0000000007ffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
VP topology {8} total 8
Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 64 bytes
percpu: Embedded 5 pages/cpu @980000000107c000 s29664 r8192 d44064 u81920
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8163
Kernel command line: clocksource=GIC console=ttyS0 printk.time=1
[    0.000000] log_buf_len individual max cpu contribution: 4096 bytes
[    0.000000] log_buf_len total cpu_extra contributions: 28672 bytes
[    0.000000] log_buf_len min size: 32768 bytes
[    0.000000] log_buf_len: 65536 bytes
[    0.000000] early log buf free: 30424(92%)
[    0.000000] PID hash table entries: 512 (order: -2, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 3, 131072
bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 2, 65536 bytes)
[    0.000000] Writing ErrCtl register=00000000
[    0.000000] Readback ErrCtl register=00000000
[    0.000000] MAAR configuration:
[    0.000000]   [0]: 0x0000000000010000-0x0000000007ffffff speculate
[    0.000000]   [1]: disabled
[    0.000000]   [2]: disabled
[    0.000000]   [3]: disabled
[    0.000000]   [4]: disabled
[    0.000000]   [5]: disabled
[    0.000000]   [6]: disabled
[    0.000000]   [7]: disabled
[    0.000000] Memory: 121104K/131072K available (5253K kernel code,
380K rwdata, 1276K rodata, 304K init, 278K bss, 9968K reserved, 0K
cma-reserved)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 64.
[    0.000000] NR_IRQS:256
[    0.000000] CPU frequency 200.00 MHz
[    0.000000] GIC frequency 99.99 MHz
[    0.000000] clocksource: GIC: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19113957547 ns
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112610963 ns
[    0.000741] sched_clock: 32 bits at 99MHz, resolution 10ns, wraps
every 21474843642ns
[    0.045796] Console: colour dummy device 80x25
[    0.052754] Calibrating delay loop... 1380.35 BogoMIPS (lpj=6901760)
[    0.182166] pid_max: default: 32768 minimum: 301
[    0.188361] Mount-cache hash table entries: 2048 (order: 0, 16384 bytes)
[    0.189064] Mountpoint-cache hash table entries: 2048 (order: 0,
16384 bytes)
[   41.034804] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.036928] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.056628] CPU1 revision is: 0001a900 (MIPS I6400)
[   41.058037] FPU revision is: 20f30300
[   41.058156] MSA revision is: 00000300
[    0.535401] Synchronize counters for CPU 1: done.
[   41.018777] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.018795] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.019379] CPU2 revision is: 0001a900 (MIPS I6400)
[   41.019391] FPU revision is: 20f30300
[   41.019397] MSA revision is: 00000300
[    0.628295] Synchronize counters for CPU 2: done.
[   41.018747] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.018763] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.019222] CPU3 revision is: 0001a900 (MIPS I6400)
[   41.019233] FPU revision is: 20f30300
[   41.019238] MSA revision is: 00000300
[    0.769903] Synchronize counters for CPU 3: done.
[   41.018757] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.018774] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.019008] CPU4 revision is: 0001a900 (MIPS I6400)
[   41.019020] FPU revision is: 20f30300
[   41.019026] MSA revision is: 00000300
[    0.911756] Synchronize counters for CPU 4: done.
[   41.018736] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.018756] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.018990] CPU5 revision is: 0001a900 (MIPS I6400)
[   41.019002] FPU revision is: 20f30300
[   41.019009] MSA revision is: 00000300
[    1.043787] Synchronize counters for CPU 5: done.
[   41.018734] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.018752] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.018977] CPU6 revision is: 0001a900 (MIPS I6400)
[   41.018989] FPU revision is: 20f30300
[   41.018995] MSA revision is: 00000300
[    1.085417] Synchronize counters for CPU 6: done.
[   41.018723] Primary instruction cache 64kB, VIPT, 4-way, linesize 64
bytes.
[   41.018742] Primary data cache 64kB, 4-way, VIPT, no aliases,
linesize 64 bytes
[   41.019068] CPU7 revision is: 0001a900 (MIPS I6400)
[   41.019080] FPU revision is: 20f30300
[   41.019085] MSA revision is: 00000300
[    1.226464] Synchronize counters for CPU 7: done.
[    1.227129] Brought up 8 CPUs
[    1.297485] devtmpfs: initialized
[    1.383773] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462750000 ns
[    1.498275] NET: Registered protocol family 16
[    1.535531] pm-cps: CPC does not support clock gating
[    1.558214] ------------[ cut here ]------------
[    1.560406] WARNING: CPU: 0 PID: 1 at fs/kernfs/dir.c:502
__kernfs_remove+0x250/0x258
[    1.561507] Modules linked in:
[   22.727193] INFO: rcu_sched self-detected stall on CPU
[   22.728201]  0-...: (2099 ticks this GP) idle=051/140000000000001/0
softirq=14/14 fqs=2085
[   22.728694]   (t=2100 jiffies g=-292 c=-293 q=134)
[   22.729734] Task dump for CPU 0:
[   22.730579] swapper/0       R  running task        0     1      0
0x00100004
[   22.731798] Stack : 000000000000001d 0000000000000004
ffffffff80790000 ffffffff80820000
          0000000000000000 0000000000000000 000000000000001d
0000000000000002
          ffffffff80820000 ffffffff80170c70 0000000000000000
0000000000000000
          0000000000000000 ffffffff80822328 0000000000000001
0000000000000002
          9800000007066fc0 ffffffff8078e340 ffffffff80780000
0000000000000000
          0000000000000000 ffffffff80780000 ffffffff80781010
0000000000000086
          0000000000000000 0000000000000000 0000000000000000
0000000000000000
          0000000000000000 980000000706b760 0000000000000000
ffffffff801a726c
          0000000000000000 0000000000000000 0000000000100004
9800000007066fc0
          ffffffff8078e340 ffffffff8010c460 ffffffff8078e340
ffffffff801a726c
          ...
[   22.736574] Call Trace:
[   22.736932] [<ffffffff8010c460>] show_stack+0x80/0xa0
[   22.737782] [<ffffffff801a726c>] rcu_dump_cpu_stacks+0x8c/0xc8
[   22.738076] [<ffffffff801829e0>] rcu_check_callbacks+0x780/0x810
[   22.738407] [<ffffffff80185360>] update_process_times+0x38/0x70
[   22.738731] [<ffffffff80193c34>] tick_handle_periodic+0x2c/0xa8
[   22.739059] [<ffffffff804b6fe8>] gic_compare_interrupt+0x28/0x40
[   22.739356] [<ffffffff80177688>] handle_percpu_devid_irq+0xa0/0xf0
[   22.739655] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
[   22.740096] [<ffffffff80375d70>] gic_irq_dispatch+0x80/0x268
[   22.740371] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
[   22.740647] [<ffffffff80108010>] do_IRQ+0x18/0x28
[   22.740879] [<ffffffff803746c4>] plat_irq_dispatch+0x64/0xa0
[   22.741158] [<ffffffff80106370>] ret_from_irq+0x0/0x4
[   22.741616] [<ffffffff8034573c>] dump_stack+0x6c/0xd0
[   22.741870] [<ffffffff8012d088>] __warn+0xf0/0x108
[   22.742117] [<ffffffff80269e78>] __kernfs_remove+0x250/0x258
[   22.742390] [<ffffffff8026ae38>] kernfs_remove_by_name_ns+0x48/0xb0
[   22.742689] [<ffffffff8026dc44>] remove_files.isra.0+0x44/0x98
[   22.742969] [<ffffffff8026e034>] sysfs_remove_group+0x4c/0xc0
[   22.743553] [<ffffffff807cbc18>] param_sysfs_init+0x178/0x1f0
[   22.744001] [<ffffffff80100564>] do_one_initcall+0x3c/0x148
[   22.744286] [<ffffffff807c4b38>] kernel_init_freeable+0x15c/0x210
[   22.744588] [<ffffffff80619cd0>] kernel_init+0x10/0xf8
[   22.744841] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[   22.745542]
[   86.443882] INFO: rcu_sched self-detected stall on CPU
[   86.444599]  0-...: (8402 ticks this GP) idle=051/140000000000001/0
softirq=14/14 fqs=7208
[   86.445336]   (t=8403 jiffies g=-292 c=-293 q=134)
[   86.446122] rcu_sched kthread starved for 1127 jiffies!
g18446744073709551324 c18446744073709551323 f0x0 RCU_GP_WAIT_FQS(3)
->state=0x0
[   86.447172] rcu_sched       R  running task        0     7      2
0x00100000
[   86.447843] Stack : ffffffff8017f140 98000000070afd68
98000000070afd50 ffffffff80781010
          98000000070afce0 98000000010f6600 00000000ffffa7cd
98000000010f6600
          98000000010f6600 ffffffff80780000 ffffffff80781010
ffffffff80790000
          0000000000000000 0000000000000001 0000000000000003
ffffffff8061b2b4
          0000000000000000 ffffffff8061dbac 0000000000000200
0000000000000000
          00000000ffffa7cd ffffffff80183fa8 98000000070ab000
ffffffff00000006
          0000000000000001 ffffffff80780000 ffffffff8078e340
ffffffff8078e340
          ffffffff8078e5a0 ffffffff80780000 ffffffff80780000
ffffffff80181a98
          98000000070ab000 ffffffff8078e5a8 ffffffff8078e5a8
0000000000000001
          0000000000000000 ffffffff80180000 ffffffff8017f140
ffffffff806e0000
          ...
[   86.452980] Call Trace:
[   86.453240] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
[   86.453728] [<ffffffff8061b2b4>] schedule+0x24/0x80
[   86.454571] [<ffffffff8061dbac>] schedule_timeout+0x11c/0x1e0
[   86.455103] [<ffffffff80181a98>] rcu_gp_kthread+0x510/0x948
[   86.455731] [<ffffffff8014a9c8>] kthread+0xc8/0xe0
[   86.456180] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[   86.456721]
[   86.456991] Task dump for CPU 0:
[   86.457297] swapper/0       R  running task        0     1      0
0x00100004
[   86.457956] Stack : 000000000000001d 0000000000000004
ffffffff80790000 ffffffff80820000
          0000000000000000 0000000000000000 000000000000001d
0000000000000002
          ffffffff80820000 ffffffff80170c70 0000000000000000
0000000000000000
          0000000000000000 ffffffff80822328 0000000000000001
ffffffff80822328
          9800000007066fc0 ffffffff8078e340 ffffffff80780000
0000000000000000
          0000000000000000 ffffffff80780000 ffffffff80781010
0000000000000086
          0000000000000000 0000000000000000 0000000000000000
0000000000000000
          0000000000000000 980000000706b760 0000000000000000
ffffffff801a726c
          0000000000000000 0000000000000000 0000000000100004
9800000007066fc0
          ffffffff8078e340 ffffffff8010c460 ffffffff8078e340
ffffffff801a726c
          ...
[   86.464391] Call Trace:
[   86.464637] [<ffffffff8010c460>] show_stack+0x80/0xa0
[   86.465108] [<ffffffff801a726c>] rcu_dump_cpu_stacks+0x8c/0xc8
[   86.465639] [<ffffffff801829e0>] rcu_check_callbacks+0x780/0x810
[   86.466157] [<ffffffff80185360>] update_process_times+0x38/0x70
[   86.466482] [<ffffffff80193c34>] tick_handle_periodic+0x2c/0xa8
[   86.466861] [<ffffffff804b6fe8>] gic_compare_interrupt+0x28/0x40
[   86.467198] [<ffffffff80177688>] handle_percpu_devid_irq+0xa0/0xf0
[   86.467536] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
[   86.467849] [<ffffffff80375d70>] gic_irq_dispatch+0x80/0x268
[   86.468165] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
[   86.468479] [<ffffffff80108010>] do_IRQ+0x18/0x28
[   86.468757] [<ffffffff803746c4>] plat_irq_dispatch+0x64/0xa0
[   86.469070] [<ffffffff80106370>] ret_from_irq+0x0/0x4
[   86.469358] [<ffffffff8034573c>] dump_stack+0x6c/0xd0
[   86.469638] [<ffffffff8012d088>] __warn+0xf0/0x108
[   86.469909] [<ffffffff80269e78>] __kernfs_remove+0x250/0x258
[   86.470321] [<ffffffff8026ae38>] kernfs_remove_by_name_ns+0x48/0xb0
[   86.470766] [<ffffffff8026dc44>] remove_files.isra.0+0x44/0x98
[   86.471183] [<ffffffff8026e034>] sysfs_remove_group+0x4c/0xc0
[   86.471592] [<ffffffff807cbc18>] param_sysfs_init+0x178/0x1f0
[   86.472003] [<ffffffff80100564>] do_one_initcall+0x3c/0x148
[   86.472405] [<ffffffff807c4b38>] kernel_init_freeable+0x15c/0x210
[   86.472840] [<ffffffff80619cd0>] kernel_init+0x10/0xf8
[   86.473219] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[   86.473546]
[  150.198525] INFO: rcu_sched self-detected stall on CPU
[  150.198956]  0-...: (14705 ticks this GP) idle=051/140000000000001/0
softirq=14/14 fqs=7208
[  150.199539]   (t=14706 jiffies g=-292 c=-293 q=134)
[  150.199943] rcu_sched kthread starved for 7430 jiffies!
g18446744073709551324 c18446744073709551323 f0x0 RCU_GP_WAIT_FQS(3)
->state=0x0
[  150.200850] rcu_sched       R  running task        0     7      2
0x00100000
[  150.201251] Stack : ffffffff8017f140 98000000070afd68
98000000070afd50 ffffffff80781010
          98000000070afce0 98000000010f6600 00000000ffffa7cd
98000000010f6600
          98000000010f6600 ffffffff80780000 ffffffff80781010
ffffffff80790000
          0000000000000000 0000000000000001 0000000000000003
ffffffff8061b2b4
          0000000000000000 ffffffff8061dbac 0000000000000200
0000000000000000
          00000000ffffa7cd ffffffff80183fa8 98000000070ab000
ffffffff00000006
          0000000000000001 ffffffff80780000 ffffffff8078e340
ffffffff8078e340
          ffffffff8078e5a0 ffffffff80780000 ffffffff80780000
ffffffff80181a98
          98000000070ab000 ffffffff8078e5a8 ffffffff8078e5a8
0000000000000001
          0000000000000000 ffffffff80180000 ffffffff8017f140
ffffffff806e0000
          ...
[  150.205988] Call Trace:
[  150.206198] [<ffffffff8061ae28>] __schedule+0x4c8/0x930
[  150.206588] [<ffffffff8061b2b4>] schedule+0x24/0x80
[  150.206951] [<ffffffff8061dbac>] schedule_timeout+0x11c/0x1e0
[  150.207381] [<ffffffff80181a98>] rcu_gp_kthread+0x510/0x948
[  150.207794] [<ffffffff8014a9c8>] kthread+0xc8/0xe0
[  150.208157] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[  150.208641]
[  150.208805] Task dump for CPU 0:
[  150.209047] swapper/0       R  running task        0     1      0
0x00100004
[  150.209580] Stack : 000000000000001d 0000000000000004
ffffffff80790000 ffffffff80820000
          0000000000000000 0000000000000000 000000000000001d
0000000000000002
          ffffffff80820000 ffffffff80170c70 0000000000000000
0000000000000000
          0000000000000000 ffffffff80822328 0000000000000001
ffffffff80822328
          9800000007066fc0 ffffffff8078e340 ffffffff80780000
0000000000000000
          0000000000000000 ffffffff80780000 ffffffff80781010
0000000000000086
          0000000000000000 0000000000000000 0000000000000000
0000000000000000
          0000000000000000 980000000706b760 0000000000000000
ffffffff801a726c
          0000000000000000 0000000000000000 0000000000100004
9800000007066fc0
          ffffffff8078e340 ffffffff8010c460 ffffffff8078e340
ffffffff801a726c
          ...
[  150.215207] Call Trace:
[  150.215407] [<ffffffff8010c460>] show_stack+0x80/0xa0
[  150.215782] [<ffffffff801a726c>] rcu_dump_cpu_stacks+0x8c/0xc8
[  150.216211] [<ffffffff801829e0>] rcu_check_callbacks+0x780/0x810
[  150.216646] [<ffffffff80185360>] update_process_times+0x38/0x70
[  150.217076] [<ffffffff80193c34>] tick_handle_periodic+0x2c/0xa8
[  150.217512] [<ffffffff804b6fe8>] gic_compare_interrupt+0x28/0x40
[  150.217948] [<ffffffff80177688>] handle_percpu_devid_irq+0xa0/0xf0
[  150.218400] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
[  150.218820] [<ffffffff80375d70>] gic_irq_dispatch+0x80/0x268
[  150.219240] [<ffffffff80172308>] generic_handle_irq+0x38/0x48
[  150.219660] [<ffffffff80108010>] do_IRQ+0x18/0x28
[  150.220123] [<ffffffff803746c4>] plat_irq_dispatch+0x64/0xa0
[  150.220579] [<ffffffff80106370>] ret_from_irq+0x0/0x4
[  150.220952] [<ffffffff8034573c>] dump_stack+0x6c/0xd0
[  150.221328] [<ffffffff8012d088>] __warn+0xf0/0x108
[  150.221688] [<ffffffff80269e78>] __kernfs_remove+0x250/0x258
[  150.222105] [<ffffffff8026ae38>] kernfs_remove_by_name_ns+0x48/0xb0
[  150.222565] [<ffffffff8026dc44>] remove_files.isra.0+0x44/0x98
[  150.222989] [<ffffffff8026e034>] sysfs_remove_group+0x4c/0xc0
[  150.223412] [<ffffffff807cbc18>] param_sysfs_init+0x178/0x1f0
[  150.223832] [<ffffffff80100564>] do_one_initcall+0x3c/0x148
[  150.224246] [<ffffffff807c4b38>] kernel_init_freeable+0x15c/0x210
[  150.224693] [<ffffffff80619cd0>] kernel_init+0x10/0xf8
[  150.225069] [<ffffffff801063b8>] ret_from_kernel_thread+0x14/0x1c
[  150.225506]
^C
qemu-system-mips64el: terminating on signal 2

While hanging, QEMU is using 2 cores at 100%.


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
  2020-02-01 22:07     ` Philippe Mathieu-Daudé
@ 2020-02-02  2:37       ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-02  2:37 UTC (permalink / raw)
  To: Richard Henderson, Alex Bennée
  Cc: peter.maydell, David Hildenbrand, qemu-devel,
	Wainer dos Santos Moschetta, Aleksandar Markovic, Cleber Rosa,
	Aleksandar Rikalo, Philippe Mathieu-Daudé,
	Aurelien Jarno

On 2/1/20 11:07 PM, Philippe Mathieu-Daudé wrote:
> On 2/1/20 9:12 PM, Philippe Mathieu-Daudé wrote:
>> Hi Richard,
>>
>> On 1/8/20 4:45 AM, Richard Henderson wrote:
>>> The separate suffixed functions were used to construct
>>> some do_##insn function switched on mmu_idx.  The interface
>>> is exactly identical to the *_mmuidx_ra functions.  Replace
>>> them directly and remove the constructions.
>>>
>>> Cc: Aurelien Jarno <aurelien@aurel32.net>
>>> Cc: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
>>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>
>> I'm seeing a regression since commit 7dd547e5a (however I'm not sure
>> this particular commit introduced the regression, or instead revealed it).
>>
>> I get a hang when booting a I6400 CPU on Malta:
>>
>> $ qemu-system-mips64el -cpu I6400 -serial stdio \
>>   -kernel vmlinux \
>>   -append "clocksource=GIC console=ttyS0 printk.time=1"
> 
> FYI this binary was built using:
> 
>   ./configure --target-list=mips64el-softmmu --disable-xen
> --disable-spice --disable-vnc --disable-rdma --disable-vde --disable-rbd
> --disable-smartcard --disable-libusb --disable-glusterfs --disable-tpm
> --disable-vhdx --disable-tools --disable-guest-agent --disable-docs
> --disable-vhost-vsock --extra-cflags='-Wno-format-truncation
> -Wno-stringop-truncation -Wno-address-of-packed-member'
> 
>> Linux version 4.7.0-rc1 (@859affe05464) (gcc version 6.3.0 20170516
>> (Debian 6.3.0-18) ) #2 SMP Sat Feb 1 18:16:17 UTC 2020
>> GCRs appear to have been moved (expected them at 0x1fbf8000)!
>> earlycon: uart8250 at I/O port 0x3f8 (options '38400n8')
>> bootconsole [uart8250] enabled
>> MIPS CPS SMP unable to proceed without a CM
>> CPU0 revision is: 0001a900 (MIPS I6400)
>> FPU revision is: 20f30300
>> MSA revision is: 00000300
>> MIPS: machine is mti,malta
>> Software DMA cache coherency enabled
>> Determined physical RAM map:
>>  memory: 0000000008000000 @ 0000000000000000 (usable)
>> Zone ranges:
>>   DMA      [mem 0x0000000000000000-0x0000000000ffffff]
>>   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>>   Normal   empty
>> Movable zone start for each node
>> Early memory node ranges
>>   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
>> Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
>> Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes.
>> Primary data cache 64kB, 4-way, VIPT, no aliases, linesize 64 bytes
>> percpu: Embedded 5 pages/cpu @980000000107c000 s29664 r8192 d44064 u81920
>> Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8163
>> Kernel command line: clocksource=GIC console=ttyS0 printk.time=1
>> [    0.000000] PID hash table entries: 512 (order: -2, 4096 bytes)
>> [    0.000000] Dentry cache hash table entries: 16384 (order: 3, 131072
>> bytes)
>> [    0.000000] Inode-cache hash table entries: 8192 (order: 2, 65536 bytes)
>> [    0.000000] Writing ErrCtl register=00000000
>> [    0.000000] Readback ErrCtl register=00000000
>> [    0.000000] MAAR configuration:
>> [    0.000000]   [0]: 0x0000000000010000-0x0000000007ffffff speculate
>> [    0.000000]   [1]: disabled
>> [    0.000000]   [2]: disabled
>> [    0.000000]   [3]: disabled
>> [    0.000000]   [4]: disabled
>> [    0.000000]   [5]: disabled
>> [    0.000000]   [6]: disabled
>> [    0.000000]   [7]: disabled
>> [    0.000000] Memory: 121728K/131072K available (5253K kernel code,
>> 380K rwdata, 1276K rodata, 304K init, 278K bss, 9344K reserved, 0K
>> cma-reserved)
>> [    0.000000] Hierarchical RCU implementation.
>> [    0.000000]  Build-time adjustment of leaf fanout to 64.
>> [    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
>> [    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=1
>> [    0.000000] NR_IRQS:256
>> [    0.000000] CPU frequency 200.00 MHz
>> [    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
>> 0xffffffff, max_idle_ns: 19112598155 ns
>> [    0.000223] sched_clock: 32 bits at 100MHz, resolution 9ns, wraps
>> every 21474829307ns
>> [    0.008011] Console: colour dummy device 80x25
>> [    0.012181] Calibrating delay loop... 950.27 BogoMIPS (lpj=4751360)
>> [    0.164015] pid_max: default: 32768 minimum: 301
>> [    0.165920] Mount-cache hash table entries: 2048 (order: 0, 16384 bytes)
>> [    0.166244] Mountpoint-cache hash table entries: 2048 (order: 0,
>> 16384 bytes)
>> [    0.202498] Brought up 1 CPUs
>> [    0.213199] devtmpfs: initialized
>> [    0.228877] clocksource: jiffies: mask: 0xffffffff max_cycles:
>> 0xffffffff, max_idle_ns: 19112604462750000 ns
>> [    0.236181] NET: Registered protocol family 16
>> [    0.253496] clocksource: pit: mask: 0xffffffff max_cycles:
>> 0xffffffff, max_idle_ns: 1601818034827 ns
>> [    0.254012] pm-cps: no CM, non-coherent states unavailable
>> [    0.257508] ------------[ cut here ]------------
>> [    0.258085] WARNING: CPU: 0 PID: 1 at fs/kernfs/dir.c:502
>> __kernfs_remove+0x250/0x258
>> [    0.258489] Modules linked in:
>> [   21.494186] INFO: rcu_sched detected stalls on CPUs/tasks:
>> [   21.494530]  (detected by 0, t=2102 jiffies, g=-299, c=-300, q=1)
>> [   21.494921] All QSes seen, last rcu_sched kthread activity 2101
>> (4294939419-4294937318), jiffies_till_next_fqs=1, root ->qsmask 0x0

I have been using this test:

---
class MaltaMachineI6400(Test):

    count = 15
    timeout = 50 * count

    def do_test_mips_malta_i6400_stall(self):
        """
        :avocado: tags=arch:mips64el
        :avocado: tags=machine:malta
        :avocado: tags=cpu:i6400
        """
        kernel_url = ('https://github.com/philmd/qemu-testing-blob/raw/'
                      'a5966ca4b5/mips/malta/mips64el/'
                      'vmlinux-4.7.0-rc1.I6400.gz')
        kernel_hash = '096f50c377ec5072e6a366943324622c312045f6'
        kernel_path_gz = self.fetch_asset(kernel_url,
asset_hash=kernel_hash)
        kernel_path = self.workdir + "vmlinux"
        archive.gzip_uncompress(kernel_path_gz, kernel_path)

        self.vm.set_console()
        kernel_command_line = ('printk.time=1 ' +
                               'clocksource=GIC console=tty0 console=ttyS0')
        self.vm.add_args('-kernel', kernel_path,
                         '-cpu', 'I6400',
                         '-smp', '8',
                         '-append', kernel_command_line)
        self.vm.launch()
        success_message = 'VFS: Cannot open root device "(null)"'
        wait_for_console_pattern(self, success_message,
                                 failure_message='detected stall')
        self.vm.shutdown()

    def test_mips_malta_i6400_stall(self):
        """
        :avocado: tags=arch:mips64el
        :avocado: tags=machine:malta
        :avocado: tags=cpu:i6400
        """
        logger = logging.getLogger('console')
        for i in range(self.count):
            logger.debug('\n' + '=' * 80)
            self.do_test_mips_malta_i6400_stall()
---

I started bisecting from current master to v2.9.1.

With v4.0.0 I get the stall:
console: [   23.066200] INFO: rcu_sched detected stalls on CPUs/tasks:

With v3.1.0 I couldn't.
PASS (305.11 s)

To be able to build and test multiple commits in parallel, I used the
'-p qemu_bin' option:

$ avocado --show=app,console run -t cpu:i6400 \
  -p qemu_bin=v4.0.0/mips64el-softmmu/qemu-system-mips64el \
  tests/acceptance/

Stats for the day:

$ ccache -s
stats zero time                     Sat Feb  1 13:48:09 2020
cache hit (direct)                 12001
cache hit (preprocessed)            7463
cache miss                         39856
cache hit rate                     32.81 %
called for link                    16945
called for preprocessing             187
compile failed                        65
preprocessor error                   210
couldn't find the compiler             1
unsupported compiler option          429
no input file                        293
cleanups performed                     0
files in cache                    104406
cache size                           7.9 GB

I'll stop commenting in this thread and create a launchpad bug.

Regards,

Phil.


^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX
  2020-02-01 20:12   ` Philippe Mathieu-Daudé
  2020-02-01 22:07     ` Philippe Mathieu-Daudé
@ 2020-02-02  9:20     ` Thomas Huth
  1 sibling, 0 replies; 51+ messages in thread
From: Thomas Huth @ 2020-02-02  9:20 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, Richard Henderson, Alex Bennée
  Cc: peter.maydell, David Hildenbrand, qemu-devel,
	Aleksandar Markovic, Aleksandar Rikalo,
	Philippe Mathieu-Daudé,
	Aurelien Jarno

On 01/02/2020 21.12, Philippe Mathieu-Daudé wrote:
> Hi Richard,
> 
> On 1/8/20 4:45 AM, Richard Henderson wrote:
>> The separate suffixed functions were used to construct
>> some do_##insn function switched on mmu_idx.  The interface
>> is exactly identical to the *_mmuidx_ra functions.  Replace
>> them directly and remove the constructions.
>>
>> Cc: Aurelien Jarno <aurelien@aurel32.net>
>> Cc: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> 
> I'm seeing a regression since commit 7dd547e5a (however I'm not sure
> this particular commit introduced the regression, or instead revealed it).
> 
> I get a hang when booting a I6400 CPU on Malta:
> 
> $ qemu-system-mips64el -cpu I6400 -serial stdio \
>   -kernel vmlinux \
>   -append "clocksource=GIC console=ttyS0 printk.time=1"
[...]

Thanks for the bisection, Philippe, that saved me quite a bit of time
doing it myself: The same problem also exists with the big-endian
version - this is also the commit that broke the Day 22 image of the
QEMU advent calendar 2018:

 https://www.qemu-advent-calendar.org/2018/download/day22.tar.xz

  Thomas



^ permalink raw reply	[flat|nested] 51+ messages in thread

end of thread, other threads:[~2020-02-02  9:21 UTC | newest]

Thread overview: 51+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-08  3:44 [PULL 00/41] tcg patch queue Richard Henderson
2020-01-08  3:44 ` [PULL 01/41] configure: Drop adjustment of textseg Richard Henderson
2020-01-08  3:44 ` [PULL 02/41] tcg: Remove softmmu code_gen_buffer fixed address Richard Henderson
2020-01-08  3:44 ` [PULL 03/41] configure: Do not force pie=no for non-x86 Richard Henderson
2020-01-08  3:44 ` [PULL 04/41] configure: Always detect -no-pie toolchain support Richard Henderson
2020-01-08  3:44 ` [PULL 05/41] configure: Unnest detection of -z,relro and -z,now Richard Henderson
2020-01-08  3:44 ` [PULL 06/41] configure: Override the os default with --disable-pie Richard Henderson
2020-01-08  3:44 ` [PULL 07/41] configure: Support -static-pie if requested Richard Henderson
2020-01-08  3:44 ` [PULL 08/41] target/xtensa: Use probe_access for itlb_hit_test Richard Henderson
2020-01-08  3:44 ` [PULL 09/41] cputlb: Use trace_mem_get_info instead of trace_mem_build_info Richard Henderson
2020-01-08  3:44 ` [PULL 10/41] trace: Remove trace_mem_build_info_no_se_[bl]e Richard Henderson
2020-01-08  3:44 ` [PULL 11/41] target/s390x: Include tcg.h in mem_helper.c Richard Henderson
2020-01-08  3:44 ` [PULL 12/41] target/arm: Include tcg.h in sve_helper.c Richard Henderson
2020-01-08  3:44 ` [PULL 13/41] accel/tcg: Include tcg.h in tcg-runtime.c Richard Henderson
2020-01-08  3:44 ` [PULL 14/41] linux-user: Include tcg.h in syscall.c Richard Henderson
2020-01-08  3:44 ` [PULL 15/41] linux-user: Include trace-root.h in syscall-trace.h Richard Henderson
2020-01-08  3:44 ` [PULL 16/41] plugins: Include trace/mem.h in api.c Richard Henderson
2020-01-08  3:44 ` [PULL 17/41] cputlb: Move body of cpu_ldst_template.h out of line Richard Henderson
2020-01-08  3:45 ` [PULL 18/41] translator: Use cpu_ld*_code instead of open-coding Richard Henderson
2020-01-08  3:45 ` [PULL 19/41] cputlb: Rename helper_ret_ld*_cmmu to cpu_ld*_code Richard Henderson
2020-01-08  3:45 ` [PULL 20/41] cputlb: Provide cpu_(ld,st}*_mmuidx_ra for user-only Richard Henderson
2020-01-08  3:45 ` [PULL 21/41] target/i386: Use cpu_*_mmuidx_ra instead of templates Richard Henderson
2020-01-08  3:45 ` [PULL 22/41] cputlb: Expand cpu_ldst_useronly_template.h in user-exec.c Richard Henderson
2020-01-08  3:45 ` [PULL 23/41] target/nios2: Remove MMU_MODE{0,1}_SUFFIX Richard Henderson
2020-01-08  3:45 ` [PULL 24/41] target/alpha: " Richard Henderson
2020-01-08  3:45 ` [PULL 25/41] target/cris: " Richard Henderson
2020-01-08  3:45 ` [PULL 26/41] target/i386: Remove MMU_MODE{0,1,2}_SUFFIX Richard Henderson
2020-01-08  3:45 ` [PULL 27/41] target/microblaze: " Richard Henderson
2020-01-08  3:45 ` [PULL 28/41] target/sh4: Remove MMU_MODE{0,1}_SUFFIX Richard Henderson
2020-01-08  3:45 ` [PULL 29/41] target/unicore32: " Richard Henderson
2020-01-08  3:45 ` [PULL 30/41] target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIX Richard Henderson
2020-01-08  3:45 ` [PULL 31/41] target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0, 1}_SUFFIX Richard Henderson
2020-01-08  3:45 ` [PULL 32/41] target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX Richard Henderson
2020-02-01 20:12   ` Philippe Mathieu-Daudé
2020-02-01 22:07     ` Philippe Mathieu-Daudé
2020-02-02  2:37       ` Philippe Mathieu-Daudé
2020-02-02  9:20     ` Thomas Huth
2020-01-08  3:45 ` [PULL 33/41] target/s390x: " Richard Henderson
2020-01-08  3:45 ` [PULL 34/41] target/ppc: " Richard Henderson
2020-01-08  3:45 ` [PULL 35/41] cputlb: Remove support for MMU_MODE*_SUFFIX Richard Henderson
2020-01-08  3:45 ` [PULL 36/41] cputlb: Expand cpu_ldst_template.h in cputlb.c Richard Henderson
2020-01-08  3:45 ` [PULL 37/41] tcg: Search includes from the project root source directory Richard Henderson
2020-01-08  3:45 ` [PULL 38/41] tcg: Search includes in the parent " Richard Henderson
2020-01-08  3:45 ` [PULL 39/41] tcg: Move TCG headers to include/tcg/ Richard Henderson
2020-01-08  3:45 ` [PULL 40/41] configure: Remove tcg/ from the preprocessor include search list Richard Henderson
2020-01-08  3:45 ` [PULL 41/41] MAINTAINERS: Replace Claudio Fontana for tcg/aarch64 Richard Henderson
2020-01-10 15:51 ` [PULL 00/41] tcg patch queue Peter Maydell
2020-01-13 21:10   ` Richard Henderson
2020-01-13 21:50     ` Richard Henderson
2020-01-13 22:06       ` Richard Henderson
2020-01-14  1:16         ` Richard Henderson

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