From: Peter Maydell <peter.maydell@linaro.org>
To: Christoffer Dall <cdall@linaro.org>
Cc: Eric Auger <eric.auger@redhat.com>,
eric.auger.pro@gmail.com,
lkml - Kernel Mailing List <linux-kernel@vger.kernel.org>,
kvm-devel <kvm@vger.kernel.org>,
Marc Zyngier <marc.zyngier@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
wanghaibin.wang@huawei.com, wu.wubin@huawei.com
Subject: Re: [PATCH 7/9] KVM: arm/arm64: vgic-its: free caches when GITS_BASER Valid bit is cleared
Date: Mon, 16 Oct 2017 10:47:35 +0100 [thread overview]
Message-ID: <CAFEAcA9Rwxz5ddyr6P7SDF_-do7TPQrdKxSRKe8eY=JEeBWTgA@mail.gmail.com> (raw)
In-Reply-To: <20171016092624.GA1845@lvm>
On 16 October 2017 at 10:26, Christoffer Dall <cdall@linaro.org> wrote:
> Hi Eric,
>
> On Mon, Sep 25, 2017 at 03:34:36PM +0200, Eric Auger wrote:
>> When the GITS_BASER<n>.Valid gets cleared, the data structures in
>> guest RAM are not provisionned anymore. The device, collection
>> and LPI lists stored in the in-kernel ITS represent the same
>> information in some form of cache. So let's void the cache.
>
> Just a thought. What about the opposite case, if the BASERs were
> previously not valid, and then become valid, is the ITS expected restore
> the state from memory?
Architecturally speaking, it's a cache. As soon as the guest
turns the GITS_CTLR.Enabled bit on, the ITS is permitted to
start reading from the tables. It's an implementation choice
whether it wants to preload a bunch of stuff, only load it
up when it becomes necessary or even leave it all in memory
and cache nothing.
Eric wrote:
> Also the spec does not mandate clearing the cache when BASER
> moves to invalid (which this patch does), although this would
> have made sense to me.
The spec says that messing with GITS_BASER while GITS_CTRL.Enabled
is set or GITS_CTLR.Quiescent is 0 is UNPREDICTABLE. And it
says that once the OS has done the Enabled/Quiescent handshake
then the ITS must have written out any dirty data to memory
and stopped doing anything. So the effect is that BASER
can't ever move to invalid while the caches are dirty.
thanks
-- PMM
next prev parent reply other threads:[~2017-10-16 9:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-25 13:34 [PATCH 0/9] vITS Migration fixes and reset Eric Auger
2017-09-25 13:34 ` [PATCH 1/9] KVM: arm/arm64: vgic-its: fix return value for restore Eric Auger
2017-09-25 13:34 ` [PATCH 2/9] KVM: arm/arm64: vgic-its: Always allow clearing GITS_CREADR/CWRITER Eric Auger
2017-09-25 13:34 ` [PATCH 3/9] KVM: arm/arm64: vgic-its: Improve error reporting on device table save Eric Auger
2017-09-25 13:34 ` [PATCH 4/9] KVM: arm/arm64: vgic-its: Check GITS_BASER Valid bit before saving tables Eric Auger
2017-09-25 13:34 ` [PATCH 5/9] KVM: arm/arm64: vgic-its: Check GITS_CBASER validity before processing commands Eric Auger
2017-09-25 13:34 ` [PATCH 6/9] KVM: arm/arm64: vgic-its: new helper functions to free the caches Eric Auger
2017-09-25 13:34 ` [PATCH 7/9] KVM: arm/arm64: vgic-its: free caches when GITS_BASER Valid bit is cleared Eric Auger
2017-10-16 9:26 ` Christoffer Dall
2017-10-16 9:44 ` Auger Eric
2017-10-16 9:59 ` Christoffer Dall
2017-10-16 9:47 ` Peter Maydell [this message]
2017-10-16 10:01 ` Christoffer Dall
2017-09-25 13:34 ` [PATCH 8/9] KVM: arm/arm64: Document KVM_DEV_ARM_ITS_CTRL_RESET Eric Auger
2017-09-25 13:34 ` [PATCH 9/9] KVM: arm/arm64: vgic-its: Implement KVM_DEV_ARM_ITS_CTRL_RESET Eric Auger
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