From: Peter Maydell <peter.maydell@linaro.org>
To: Michael Clark <mjc@sifive.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
RISC-V Patches <patches@groups.riscv.org>
Subject: Re: [Qemu-devel] [PULL 0/2] RISC-V: Important fixes for QEMU 2.12
Date: Thu, 29 Mar 2018 11:21:24 +0100 [thread overview]
Message-ID: <CAFEAcA9VVr-2DBDBUK6gq8+2B6xtruqqGA=d6WqfwC6jxwV5dA@mail.gmail.com> (raw)
In-Reply-To: <1522269619-48636-1-git-send-email-mjc@sifive.com>
On 28 March 2018 at 21:40, Michael Clark <mjc@sifive.com> wrote:
> The following changes since commit 043289bef4d9c0d277c45695c676a6cc9fca48a0:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180328' into staging (2018-03-28 13:30:10 +0100)
>
> are available in the git repository at:
>
> https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-2.12-important-fixes
>
> for you to fetch changes up to 33b4f859f1e1ea6722d10c3e9c0e3d85afb44ff4:
>
> RISC-V: Fix incorrect disassembly for addiw (2018-03-28 11:12:02 -0700)
>
> ----------------------------------------------------------------
> RISC-V: Important fixes for QEMU 2.12
>
> This series includes changes that are considered important.
> i.e. correct user-visible bugs that are exercised by common
> operations such as -cpu list (CPU model changes) or -d in_asm
> (fix for disassembly of addiw)
>
> ----------------------------------------------------------------
> Michael Clark (2):
> RISC-V: Convert cpu definition to future model
> RISC-V: Fix incorrect disassembly for addiw
>
> disas/riscv.c | 2 +-
> target/riscv/cpu.c | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------------
> 2 files changed, 70 insertions(+), 55 deletions(-)
Applied, thanks.
-- PMM
prev parent reply other threads:[~2018-03-29 10:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-28 20:40 [Qemu-devel] [PULL 0/2] RISC-V: Important fixes for QEMU 2.12 Michael Clark
2018-03-28 20:40 ` [Qemu-devel] [PULL 1/2] RISC-V: Convert cpu definition to future model Michael Clark
2018-03-28 20:40 ` [Qemu-devel] [PULL 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
2018-03-29 10:21 ` Peter Maydell [this message]
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