Re: [Qemu-devel] [RFC PATCH 0/3] pflash_cfi01: allow reading/writing it only in secure mode

From: Peter Maydell <peter.maydell@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
	Laszlo Ersek <lersek@redhat.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Gerd Hoffmann <kraxel@redhat.com>
Subject: Re: [Qemu-devel] [RFC PATCH 0/3] pflash_cfi01: allow reading/writing it only in secure mode
Date: Thu, 9 Apr 2015 13:47:50 +0100	[thread overview]
Message-ID: <CAFEAcA9WZ5Vx3tRVrykP33+JSq-A=a+-fMRMPR-PJnGaHazmtg@mail.gmail.com> (raw)
In-Reply-To: <1428582043-19080-1-git-send-email-pbonzini@redhat.com>

On 9 April 2015 at 13:20, Paolo Bonzini <pbonzini@redhat.com> wrote:
> This is an example of usage of attributes in a device model.  It lets
> you block flash writes unless the CPU is in secure mode.  Enabling it
> currently requires a -readconfig file:
>
>         [global]
>         driver = "cfi.pflash01"
>         property = "secure"
>         value = "on"
>
> because the driver includes a "."; however, I plan to enable this through
> the command line for the final version of the patches.

Are real flash devices ever wired up like this?
I would expect boards which want to provide secure-mode
only flash to do so by not giving any access at all to
the device from the non-secure address space.

(Supporting multiple AddressSpaces for ARM CPUs is the
next thing on my todo list; as well as partitioning the
flash this would allow secure-mode-only RAM and UARTs,
for instance.)

-- PMM