* [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019
@ 2019-08-29 10:24 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
` (31 more replies)
0 siblings, 32 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
The following changes since commit 1b142da5f82a8fcdc7783a418592de654d5c6052:
target/mips: Clean up handling of CP0 register 0 (2019-08-29 11:50:18 +0200)
are available in the git repository at:
https://github.com/AMarkovic/qemu tags/mips-queue-aug-29-2019
for you to fetch changes up to abd4393d769d9fe2333b2e83e00f911a78475943:
target/mips: Fix emulation of ST.W in system mode (2019-08-29 12:11:14 +0200)
----------------------------------------------------------------
MIPS queue for August 29th, 2019
Highlights:
- cleanup of handling of configuration register CP0
- fix for ST.W emulation (in system mode only)
----------------------------------------------------------------
Aleksandar Markovic (31):
target/mips: Clean up handling of CP0 register 0
target/mips: Clean up handling of CP0 register 1
target/mips: Clean up handling of CP0 register 2
target/mips: Clean up handling of CP0 register 3
target/mips: Clean up handling of CP0 register 4
target/mips: Clean up handling of CP0 register 5
target/mips: Clean up handling of CP0 register 6
target/mips: Clean up handling of CP0 register 7
target/mips: Clean up handling of CP0 register 8
target/mips: Clean up handling of CP0 register 9
target/mips: Clean up handling of CP0 register 10
target/mips: Clean up handling of CP0 register 11
target/mips: Clean up handling of CP0 register 12
target/mips: Clean up handling of CP0 register 13
target/mips: Clean up handling of CP0 register 14
target/mips: Clean up handling of CP0 register 15
target/mips: Clean up handling of CP0 register 16
target/mips: Clean up handling of CP0 register 17
target/mips: Clean up handling of CP0 register 18
target/mips: Clean up handling of CP0 register 19
target/mips: Clean up handling of CP0 register 20
target/mips: Clean up handling of CP0 register 23
target/mips: Clean up handling of CP0 register 24
target/mips: Clean up handling of CP0 register 25
target/mips: Clean up handling of CP0 register 26
target/mips: Clean up handling of CP0 register 27
target/mips: Clean up handling of CP0 register 28
target/mips: Clean up handling of CP0 register 29
target/mips: Clean up handling of CP0 register 30
target/mips: Clean up handling of CP0 register 31
target/mips: Fix emulation of ST.W in system mode
target/mips/cpu.h | 113 ++++-
target/mips/op_helper.c | 16 +-
target/mips/translate.c | 1142 ++++++++++++++++++++++++-----------------------
3 files changed, 685 insertions(+), 586 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
` (30 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 0.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-2-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 40 ++++++++++++++++++++--------------------
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1fd4a18..42d0e44 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -277,6 +277,9 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
+#define CP0_REG00__MVPCONTROL 1
+#define CP0_REG00__MVPCONF0 2
+#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
/* CP0 Register 02 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8ebde6f..c3fcfb4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6813,26 +6813,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -7573,26 +7573,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -8319,26 +8319,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -9033,26 +9033,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
` (29 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 1.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-3-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 8 +++++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 42d0e44..36e983a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -282,6 +282,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
+#define CP0_REG01__RANDOM 0
+#define CP0_REG01__VPECONTROL 1
+#define CP0_REG01__VPECONF0 2
+#define CP0_REG01__VPECONF1 3
+#define CP0_REG01__YQMASK 4
+#define CP0_REG01__VPESCHEDULE 5
+#define CP0_REG01__VPESCHEFBACK 6
+#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
/* CP0 Register 03 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c3fcfb4..97e0aec 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6843,42 +6843,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -7603,43 +7603,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
@@ -8349,42 +8349,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -9063,41 +9063,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
` (28 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 2.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-4-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 7 ++++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 36e983a..466f72a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -292,6 +292,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
+#define CP0_REG02__TCSTATUS 1
+#define CP0_REG02__TCBIND 2
+#define CP0_REG02__TCRESTART 3
+#define CP0_REG02__TCHALT 4
+#define CP0_REG02__TCCONTEXT 5
+#define CP0_REG02__TCSCHEDULE 6
+#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 97e0aec..66c6207 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6889,7 +6889,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6906,37 +6906,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -7650,41 +7650,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
@@ -8395,41 +8395,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -9108,41 +9108,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (2 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
` (27 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 3.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-5-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 466f72a..d5b7103 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -302,6 +302,7 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1
+#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
#define CP0_REG04__USERLOCAL 2
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 66c6207..059f53e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6647,7 +6647,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
@@ -6728,7 +6728,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
@@ -6947,7 +6947,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6964,7 +6964,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -7695,11 +7695,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
gen_helper_mtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
@@ -8440,11 +8440,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -9153,11 +9153,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
gen_helper_dmtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (3 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
` (26 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 4.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-6-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 36 ++++++++++++++++++++----------------
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d5b7103..496872e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -305,7 +305,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
+#define CP0_REG04__CONTEXTCONFIG 1
#define CP0_REG04__USERLOCAL 2
+#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID 4
#define CP0_REG00__MMID 5
/* CP0 Register 05 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 059f53e..9df59f1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6975,16 +6975,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
- case 1:
- /* gen_helper_mfc0_contextconfig(arg); - SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -7710,15 +7711,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -8455,15 +8457,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
- case 1:
-// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_dmfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -9168,15 +9171,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_dmtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (4 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
` (25 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 5.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-7-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 6 +++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 496872e..ed1a974 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -313,6 +313,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1
+#define CP0_REG05__SEGCTL0 2
+#define CP0_REG05__SEGCTL1 3
+#define CP0_REG05__SEGCTL2 4
+#define CP0_REG05__PWBASE 5
+#define CP0_REG05__PWFIELD 6
+#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
/* CP0 Register 07 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9df59f1..19f86f2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6998,44 +6998,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -7732,42 +7732,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
@@ -8478,41 +8478,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -9192,41 +9192,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (5 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
` (24 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 6.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-8-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 6 ++++++
target/mips/translate.c | 56 ++++++++++++++++++++++++-------------------------
2 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index ed1a974..a0c6a6f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -321,6 +321,12 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
+#define CP0_REG06__SRSCONF0 1
+#define CP0_REG06__SRSCONF1 2
+#define CP0_REG06__SRSCONF2 3
+#define CP0_REG06__SRSCONF3 4
+#define CP0_REG06__SRSCONF4 5
+#define CP0_REG06__PWCTL 6
/* CP0 Register 07 */
#define CP0_REG07__HWRENA 0
/* CP0 Register 08 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19f86f2..a914fe4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7046,36 +7046,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -7778,36 +7778,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
@@ -8523,36 +8523,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -9237,36 +9237,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (6 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
` (23 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 7.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-9-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a914fe4..cf2ba5a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7086,7 +7086,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -7818,7 +7818,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
@@ -8563,7 +8563,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -9277,7 +9277,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (7 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
` (22 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 8.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-10-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 32 ++++++++++++++++----------------
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a0c6a6f..50a7205 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -333,6 +333,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG08__BADVADDR 0
#define CP0_REG08__BADINSTR 1
#define CP0_REG08__BADINSTRP 2
+#define CP0_REG08__BADINSTRX 3
/* CP0 Register 09 */
#define CP0_REG09__COUNT 0
#define CP0_REG09__SAARI 6
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cf2ba5a..d4faa75 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7097,22 +7097,22 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
@@ -7830,19 +7830,19 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
@@ -8574,21 +8574,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
@@ -9289,19 +9289,19 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (8 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
` (21 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 9.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-11-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d4faa75..b79c58c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6658,7 +6658,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfhc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -6740,7 +6740,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mthc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -7124,7 +7124,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -7139,12 +7139,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -7852,16 +7852,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -8600,7 +8600,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -8615,12 +8615,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_dmfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -9311,16 +9311,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (9 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
` (20 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 10.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-12-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8 ++++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 50a7205..3797bdc 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -342,6 +342,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG10__ENTRYHI 0
#define CP0_REG10__GUESTCTL1 4
#define CP0_REG10__GUESTCTL2 5
+#define CP0_REG10__GUESTCTL3 6
/* CP0 Register 11 */
#define CP0_REG11__COMPARE 0
#define CP0_REG11__GUESTCTL0EXT 4
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b79c58c..50863cf 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7155,7 +7155,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EntryHi";
@@ -7872,7 +7872,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
@@ -8631,7 +8631,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
register_name = "EntryHi";
break;
@@ -9333,7 +9333,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (10 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
` (19 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 11.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-13-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 50863cf..b5d5994 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7166,7 +7166,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -7882,7 +7882,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
@@ -8641,7 +8641,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -9343,7 +9343,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (11 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
` (18 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 12.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-14-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 32 ++++++++++++++++----------------
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3797bdc..061effb 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -350,6 +350,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__STATUS 0
#define CP0_REG12__INTCTL 1
#define CP0_REG12__SRSCTL 2
+#define CP0_REG12__SRSMAP 3
+#define CP0_REG12__VIEW_IPL 4
+#define CP0_REG12__SRSMAP2 5
#define CP0_REG12__GUESTCTL0 6
#define CP0_REG12__GTOFFSET 7
/* CP0 Register 13 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b5d5994..fb9c719 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7177,21 +7177,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -7893,7 +7893,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -7901,21 +7901,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
@@ -8652,21 +8652,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -9356,7 +9356,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -9364,21 +9364,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (12 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
` (17 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 13.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-15-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 8 ++++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 061effb..4fce05a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -357,6 +357,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__GTOFFSET 7
/* CP0 Register 13 */
#define CP0_REG13__CAUSE 0
+#define CP0_REG13__VIEW_RIPL 4
+#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
/* CP0 Register 15 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fb9c719..4da08e1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7202,7 +7202,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -7928,7 +7928,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
@@ -8677,7 +8677,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -9391,7 +9391,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (13 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
` (16 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 14.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-16-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8 ++++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4fce05a..2a9c6d5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -361,6 +361,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
+#define CP0_REG14__NESTEDEPC 2
/* CP0 Register 15 */
#define CP0_REG15__PRID 0
#define CP0_REG15__EBASE 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4da08e1..efedced 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7212,7 +7212,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EPC";
@@ -7946,7 +7946,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -8687,7 +8687,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -9409,7 +9409,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (14 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
` (15 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 15.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-17-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2a9c6d5..8ecfdb3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -367,6 +367,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index efedced..238066f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7223,17 +7223,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -7956,11 +7956,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -8697,16 +8697,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -9419,11 +9419,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (15 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
@ 2019-08-29 10:24 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
` (14 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:24 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 16.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-18-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 3 ++-
target/mips/translate.c | 60 ++++++++++++++++++++++++-------------------------
2 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 8ecfdb3..d6405ad 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -375,7 +375,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG16__CONFIG3 3
#define CP0_REG16__CONFIG4 4
#define CP0_REG16__CONFIG5 5
-#define CP0_REG00__CONFIG7 7
+#define CP0_REG16__CONFIG6 6
+#define CP0_REG16__CONFIG7 7
/* CP0 Register 17 */
#define CP0_REG17__LLADDR 0
#define CP0_REG17__MAAR 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 238066f..4808640 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7246,36 +7246,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -7971,45 +7971,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_helper_mtc0_config4(cpu_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
/* ignored */
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
/* ignored */
register_name = "Config7";
break;
@@ -8718,36 +8718,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -9434,33 +9434,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
/* currently ignored */
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (16 preceding siblings ...)
2019-08-29 10:24 ` [Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
` (13 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 17.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-19-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4808640..edeaaad 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6669,12 +6669,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
register_name = "MAAR";
@@ -6751,7 +6751,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
/*
* LLAddr is read-only (the only exception is bit 0 if LLB is
* supported); the CP0_LLAddr_rw_bitmask does not seem to be
@@ -6760,7 +6760,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
*/
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
register_name = "MAAR";
@@ -7285,16 +7285,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -8020,16 +8020,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -8757,16 +8757,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_dmfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -9474,16 +9474,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (17 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
` (12 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 18.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-20-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 20 +++++++++-------
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6405ad..d6ea111 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t;
* Register 16 Register 17 Register 18 Register 19
* ----------- ----------- ----------- -----------
*
- * 0 Config LLAddr WatchLo WatchHi
- * 1 Config1 MAAR WatchLo WatchHi
- * 2 Config2 MAARI WatchLo WatchHi
- * 3 Config3 WatchLo WatchHi
- * 4 Config4 WatchLo WatchHi
- * 5 Config5 WatchLo WatchHi
- * 6 WatchLo WatchHi
- * 7 WatchLo WatchHi
+ * 0 Config LLAddr WatchLo0 WatchHi
+ * 1 Config1 MAAR WatchLo1 WatchHi
+ * 2 Config2 MAARI WatchLo2 WatchHi
+ * 3 Config3 WatchLo3 WatchHi
+ * 4 Config4 WatchLo4 WatchHi
+ * 5 Config5 WatchLo5 WatchHi
+ * 6 WatchLo6 WatchHi
+ * 7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -386,6 +386,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG18__WATCHLO1 1
#define CP0_REG18__WATCHLO2 2
#define CP0_REG18__WATCHLO3 3
+#define CP0_REG18__WATCHLO4 4
+#define CP0_REG18__WATCHLO5 5
+#define CP0_REG18__WATCHLO6 6
+#define CP0_REG18__WATCHLO7 7
/* CP0 Register 19 */
#define CP0_REG19__WATCHHI0 0
#define CP0_REG19__WATCHHI1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index edeaaad..6a11e8d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7305,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8040,14 +8040,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8777,14 +8777,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -9494,14 +9494,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (18 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
` (11 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 19.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-21-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 4 ++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6ea111..b4866a5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -395,6 +395,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG19__WATCHHI1 1
#define CP0_REG19__WATCHHI2 2
#define CP0_REG19__WATCHHI3 3
+#define CP0_REG19__WATCHHI4 4
+#define CP0_REG19__WATCHHI5 5
+#define CP0_REG19__WATCHHI6 6
+#define CP0_REG19__WATCHHI7 7
/* CP0 Register 20 */
#define CP0_REG20__XCONTEXT 0
/* CP0 Register 21 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6a11e8d..6d617f4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7323,14 +7323,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8058,14 +8058,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8795,14 +8795,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -9512,14 +9512,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (19 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
` (10 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 20.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-22-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6d617f4..55b0005 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7341,7 +7341,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
@@ -8076,7 +8076,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
@@ -8813,7 +8813,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
register_name = "XContext";
@@ -9530,7 +9530,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
register_name = "XContext";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (20 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
` (9 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 23.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-23-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 6 +++
target/mips/translate.c | 126 +++++++++++++++++++++++++++++++-----------------
2 files changed, 89 insertions(+), 43 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b4866a5..168a6d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -405,6 +405,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 22 */
/* CP0 Register 23 */
#define CP0_REG23__DEBUG 0
+#define CP0_REG23__TRACECONTROL 1
+#define CP0_REG23__TRACECONTROL2 2
+#define CP0_REG23__USERTRACEDATA1 3
+#define CP0_REG23__TRACEIBPC 4
+#define CP0_REG23__TRACEDBPC 5
+#define CP0_REG23__DEBUG2 6
/* CP0 Register 24 */
#define CP0_REG24__DEPC 0
/* CP0 Register 25 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 55b0005..610631f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7371,25 +7371,34 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
- case 1:
-// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracecontrol(arg); */
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracecontrol2(arg); */
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
- register_name = "UserTraceData";
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_mfc0_usertracedata1(arg);*/
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
- register_name = "TraceBPC";
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mfc0_traceibpc(arg); */
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracedbpc(arg); */
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8105,38 +8114,49 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
- case 1:
-// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 2:
-// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 3:
+ case CP0_REG23__USERTRACEDATA1:
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
-// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
+ /* PDtrace support */
+ /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 4:
-// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "TraceBPC";
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8840,25 +8860,34 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
- case 1:
-// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
- register_name = "UserTraceData";
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
- register_name = "TraceBPC";
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -9557,36 +9586,47 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
- case 1:
-// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "UserTraceData";
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "TraceBPC";
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (21 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
` (8 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 24.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-24-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 610631f..515d04c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7406,7 +7406,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
@@ -8164,7 +8164,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -8895,7 +8895,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -9634,7 +9634,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (22 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
` (7 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 25.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-25-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 515d04c..84aabf6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7418,35 +7418,35 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8175,35 +8175,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8906,35 +8906,35 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_dmfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_dmfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_dmfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_dmfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_dmfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_dmfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_dmfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -9645,35 +9645,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(cpu_env, arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(cpu_env, arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(cpu_env, arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(cpu_env, arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(cpu_env, arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(cpu_env, arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(cpu_env, arg); */
register_name = "Performance7";
goto cp0_unimplemented;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (23 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
` (6 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 26.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-26-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 168a6d7..40b7cc6 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -423,7 +423,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG25__PERFCTL3 6
#define CP0_REG25__PERFCNT3 7
/* CP0 Register 26 */
-#define CP0_REG00__ERRCTL 0
+#define CP0_REG26__ERRCTL 0
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 84aabf6..a8ea952 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7456,7 +7456,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -8213,7 +8213,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
@@ -8944,7 +8944,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -9683,7 +9683,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (24 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
` (5 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 27.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-27-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a8ea952..c969c25 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7466,10 +7466,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -8224,10 +8221,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@@ -8955,10 +8949,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_27:
switch (sel) {
/* ignored */
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -9694,10 +9685,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (25 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
` (4 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 28.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-28-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 24 +++++++++++--------
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 40b7cc6..de9e850 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLo DataHi KScratch<n>
- * 3 TagLo TagHi KScratch<n>
- * 4 DataLo DataHi KScratch<n>
- * 5 TagLo TagHi KScratch<n>
- * 6 DataLo DataHi KScratch<n>
- * 7 TagLo TagHi KScratch<n>
+ * 2 DataLo1 DataHi KScratch<n>
+ * 3 TagLo1 TagHi KScratch<n>
+ * 4 DataLo2 DataHi KScratch<n>
+ * 5 TagLo2 TagHi KScratch<n>
+ * 6 DataLo3 DataHi KScratch<n>
+ * 7 TagLo3 TagHi KScratch<n>
*
*/
#define CP0_REGISTER_00 0
@@ -427,10 +427,14 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
-#define CP0_REG28__ITAGLO 0
-#define CP0_REG28__IDATALO 1
-#define CP0_REG28__DTAGLO 2
-#define CP0_REG28__DDATALO 3
+#define CP0_REG28__TAGLO 0
+#define CP0_REG28__DATALO 1
+#define CP0_REG28__TAGLO1 2
+#define CP0_REG28__DATALO1 3
+#define CP0_REG28__TAGLO2 4
+#define CP0_REG28__DATALO2 5
+#define CP0_REG28__TAGLO3 6
+#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
#define CP0_REG29__IDATAHI 1
#define CP0_REG29__DDATAHI 3
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c969c25..032e3b0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7476,10 +7476,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
@@ -7488,10 +7488,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -8231,17 +8231,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
@@ -8959,17 +8959,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -9695,17 +9695,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (26 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
` (3 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 29.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-29-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 22 ++++++++++-------
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 46 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index de9e850..6defbea 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLo1 DataHi KScratch<n>
- * 3 TagLo1 TagHi KScratch<n>
- * 4 DataLo2 DataHi KScratch<n>
- * 5 TagLo2 TagHi KScratch<n>
- * 6 DataLo3 DataHi KScratch<n>
- * 7 TagLo3 TagHi KScratch<n>
+ * 2 DataLo1 DataHi1 KScratch<n>
+ * 3 TagLo1 TagHi1 KScratch<n>
+ * 4 DataLo2 DataHi2 KScratch<n>
+ * 5 TagLo2 TagHi2 KScratch<n>
+ * 6 DataLo3 DataHi3 KScratch<n>
+ * 7 TagLo3 TagHi3 KScratch<n>
*
*/
#define CP0_REGISTER_00 0
@@ -436,8 +436,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG28__TAGLO3 6
#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
-#define CP0_REG29__IDATAHI 1
-#define CP0_REG29__DDATAHI 3
+#define CP0_REG29__TAGHI 0
+#define CP0_REG29__DATAHI 1
+#define CP0_REG29__TAGHI1 2
+#define CP0_REG29__DATAHI1 3
+#define CP0_REG29__TAGHI2 4
+#define CP0_REG29__DATAHI2 5
+#define CP0_REG29__TAGHI3 6
+#define CP0_REG29__DATAHI3 7
/* CP0 Register 30 */
#define CP0_REG30__ERROREPC 0
/* CP0 Register 31 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 032e3b0..6d6fda6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7501,17 +7501,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -8251,17 +8251,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
@@ -8979,17 +8979,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -9715,17 +9715,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (27 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
` (2 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 30.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-30-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6d6fda6..93f7a20 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7521,7 +7521,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "ErrorEPC";
@@ -8272,7 +8272,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -8999,7 +8999,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -9736,7 +9736,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (28 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode Aleksandar Markovic
2019-09-04 10:24 ` [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Peter Maydell
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 31.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-31-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 56 ++++++++++++++++++++++++-------------------------
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6defbea..ca00f41 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -613,7 +613,6 @@ struct CPUMIPSState {
* CP0 Register 4
*/
target_ulong CP0_Context;
- target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
@@ -1024,6 +1023,7 @@ struct CPUMIPSState {
* CP0 Register 31
*/
int32_t CP0_DESAVE;
+ target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 93f7a20..f6d1424 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7532,17 +7532,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -8282,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9009,17 +9009,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9746,17 +9746,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (29 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
@ 2019-08-29 10:25 ` Aleksandar Markovic
2019-09-04 10:24 ` [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Peter Maydell
31 siblings, 0 replies; 33+ messages in thread
From: Aleksandar Markovic @ 2019-08-29 10:25 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Order of arguments in helper_ret_stl_mmu() invocations was wrong,
apparently caused by a misplaced multiline copy-and-paste.
Fixes: 6decc57 ("target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host")
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1567009239-11273-1-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/op_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index f88a3ab..5b8bb20 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4692,15 +4692,15 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
ensure_writable_pages(env, addr, mmu_idx, GETPC());
#if !defined(CONFIG_USER_ONLY)
#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
#else
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
#endif
#else
#if !defined(HOST_WORDS_BIGENDIAN)
--
2.7.4
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
` (30 preceding siblings ...)
2019-08-29 10:25 ` [Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode Aleksandar Markovic
@ 2019-09-04 10:24 ` Peter Maydell
31 siblings, 0 replies; 33+ messages in thread
From: Peter Maydell @ 2019-09-04 10:24 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: QEMU Developers, Aleksandar Markovic
On Thu, 29 Aug 2019 at 11:25, Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> The following changes since commit 1b142da5f82a8fcdc7783a418592de654d5c6052:
>
> target/mips: Clean up handling of CP0 register 0 (2019-08-29 11:50:18 +0200)
>
> are available in the git repository at:
>
> https://github.com/AMarkovic/qemu tags/mips-queue-aug-29-2019
>
> for you to fetch changes up to abd4393d769d9fe2333b2e83e00f911a78475943:
>
> target/mips: Fix emulation of ST.W in system mode (2019-08-29 12:11:14 +0200)
>
> ----------------------------------------------------------------
>
> MIPS queue for August 29th, 2019
>
> Highlights:
>
> - cleanup of handling of configuration register CP0
> - fix for ST.W emulation (in system mode only)
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2019-09-04 10:26 UTC | newest]
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2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
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2019-08-29 10:24 ` [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode Aleksandar Markovic
2019-09-04 10:24 ` [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Peter Maydell
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