From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZCTS7-0001Nh-C1 for qemu-devel@nongnu.org; Tue, 07 Jul 2015 10:02:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZCTRz-0005rE-Fu for qemu-devel@nongnu.org; Tue, 07 Jul 2015 10:02:27 -0400 Received: from mail-vn0-f53.google.com ([209.85.216.53]:35780) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZCTRz-0005qc-8y for qemu-devel@nongnu.org; Tue, 07 Jul 2015 10:02:19 -0400 Received: by vnbg190 with SMTP id g190so27400622vnb.2 for ; Tue, 07 Jul 2015 07:02:19 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1434419515-3572-3-git-send-email-edgar.iglesias@gmail.com> References: <1434419515-3572-1-git-send-email-edgar.iglesias@gmail.com> <1434419515-3572-3-git-send-email-edgar.iglesias@gmail.com> From: Peter Maydell Date: Tue, 7 Jul 2015 14:55:52 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v5 2/6] target-arm: Add CNTHCTL_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: Edgar Iglesias , Sergey Fedorov , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Alexander Graf On 16 June 2015 at 02:51, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Adds control for trapping selected timer and counter accesses to EL2. > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 34 ++++++++++++++++++++++++++++++++-- > 2 files changed, 33 insertions(+), 2 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 1a66aa4..f39c32b 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -355,6 +355,7 @@ typedef struct CPUARMState { > }; > uint64_t c14_cntfrq; /* Counter Frequency register */ > uint64_t c14_cntkctl; /* Timer Control register */ > + uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ > uint64_t cntvoff_el2; /* Counter Virtual Offset register */ > ARMGenericTimer c14_timer[NUM_GTIMERS]; > uint32_t c15_cpar; /* XScale Coprocessor Access Register */ > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 41cfad8..282f9fb 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1153,23 +1153,42 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) > > static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) > { > + unsigned int cur_el = arm_current_el(env); > + bool secure = arm_is_secure(env); > + > /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ > - if (arm_current_el(env) == 0 && > + if (cur_el == 0 && > !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { > return CP_ACCESS_TRAP; > } > + > + if (arm_feature(env, ARM_FEATURE_EL2) && > + timeridx == GTIMER_PHYS && !secure && cur_el < 2 && > + !extract32(env->cp15.cnthctl_el2, 0, 1)) { > + return CP_ACCESS_TRAP_EL2; > + } > return CP_ACCESS_OK; > } > > static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) > { > + unsigned int cur_el = arm_current_el(env); > + bool secure = arm_is_secure(env); > + > /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if > * EL0[PV]TEN is zero. > */ > - if (arm_current_el(env) == 0 && > + if (cur_el == 0 && > !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { > return CP_ACCESS_TRAP; > } > + > + if (arm_feature(env, ARM_FEATURE_EL2)) { > + if (timeridx == GTIMER_PHYS && !secure && cur_el < 2 && > + !extract32(env->cp15.cnthctl_el2, 1, 1)) { > + return CP_ACCESS_TRAP_EL2; > + } > + } It would be nice to be consistent about how we lay this conditional out with the near-equivalent one in the previous function... > return CP_ACCESS_OK; > } > > @@ -2557,6 +2576,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, > .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, > .resetvalue = 0 }, > + { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, > + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > @@ -2676,6 +2698,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .type = ARM_CP_NO_RAW, .access = PL2_W, > .writefn = tlbi_aa64_vaa_write }, > #ifndef CONFIG_USER_ONLY > + { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, > + /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the > + * reset values as IMPDEF. We chose to reset to 3 to comply with "choose". > + * both ARMv7 and ARMv8. > + */ > + .access = PL2_RW, .resetvalue = 3, > + .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, > { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, > .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, Otherwise Reviewed-by: Peter Maydell thanks -- PMM