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From: Peter Maydell <peter.maydell@linaro.org>
To: Guenter Roeck <linux@roeck-us.net>
Cc: Igor Mitsyanko <i.mitsyanko@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 5/7] hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts
Date: Mon, 20 Jan 2020 13:58:44 +0000	[thread overview]
Message-ID: <CAFEAcA9kK7mK=FQRKc0sDL8rZzibYov9Xm__+-MA06ERCotZ1Q@mail.gmail.com> (raw)
In-Reply-To: <20200118164229.22539-6-linux@roeck-us.net>

On Sat, 18 Jan 2020 at 16:42, Guenter Roeck <linux@roeck-us.net> wrote:
>
> The driver already implements a receive FIFO, but it does not
> handle receive FIFO trigger levels and timeout. Implement the
> missing functionality.
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> ---
> v2: Call exynos4210_uart_rx_timeout_set() from new post_load function
>     to set the receive timeout timer.
>     Add timer to vmstate_exynos4210_uart.
>
>  hw/char/exynos4210_uart.c | 122 ++++++++++++++++++++++++++++++--------
>  hw/char/trace-events      |   3 +-
>  2 files changed, 99 insertions(+), 26 deletions(-)

Since the timeout value depends on s->wordtime, and
exynos4210_uart_update_parameters() can change s->wordtime,
do you need to recalculate the timeout at that point?
This would correspond to if the guest wrote to the
UBRDIV/UFRACVAL/ULCON registers, I think. Maybe this comes
under the heading of "undefined behaviour if the guest does
this odd thing" ? (The exact behaviour of the h/w is probably
undocumented and mildly painful to emulate exactly, so it's
hard to see why QEMU should care about getting it exactly right.)

I did also wonder whether writing the same value to the UCON
timeout-interval field repeatedly really does restart the timer
counting down from 8*(N+1) frames again, but again maybe that's
just weird for a guest to do.

> @@ -553,6 +620,7 @@ static const VMStateDescription vmstate_exynos4210_uart = {
>                         vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
>          VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
>                               EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
> +        VMSTATE_TIMER_PTR(fifo_timeout_timer, Exynos4210UartState),
>          VMSTATE_END_OF_LIST()
>      }
>  };

Unfortunately you can't simply add entries to a VMStateDescription:
it breaks migration compatibility.

The choices here are:
 * the nicest approach if it works is that in the post_load
function you just recalculate the timer timeout. Then there's
no need to migrate the current state of the timer. (In fact
it looks like your code does do this in post_load.)
 * if something really does need adding to the migration state,
then the version_id and minimum_version_id need to be bumped
(so migration fails cleanly rather than confusingly).
 * if you want migration to continue to work across versions
(which we don't care about for the exynos boards but does
apply for boards like 'virt'), this can be done by adding
a 'subsection' to the vmstate.

I think the answer in this case is just "you don't need to
add this line to the vmstate at all". (This does mean that
a vmsave/vmload will slightly extend the rx-timeout and
delay the interrupt because we re-calculate the timer,
but I guess that's OK. If you don't like that and would
prefer the timer to retain the exact timeout value across
migration, then keep the new vmstate array entry, bump the
version fields, and don't call exynos4210_uart_rx_timeout_set()
in post-load.)

thanks
-- PMM


  reply	other threads:[~2020-01-20 13:59 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-18 16:42 [PATCH v2 0/7] Fix Exynos4210 DMA support Guenter Roeck
2020-01-18 16:42 ` [PATCH v2 1/7] dma/pl330: Convert to support tracing Guenter Roeck
2020-01-20 13:28   ` Peter Maydell
2020-01-18 16:42 ` [PATCH v2 2/7] hw/arm/exynos4210: Fix DMA initialization Guenter Roeck
2020-01-20 13:35   ` Peter Maydell
2020-01-20 14:30     ` Guenter Roeck
2020-01-20 14:46       ` Peter Maydell
2020-01-20 15:11         ` Guenter Roeck
2020-01-18 16:42 ` [PATCH v2 3/7] hw/char/exynos4210_uart: Convert to support tracing Guenter Roeck
2020-01-18 16:42 ` [PATCH v2 4/7] hw/char/exynos4210_uart: Implement post_load function Guenter Roeck
2020-01-20 13:29   ` Peter Maydell
2020-01-18 16:42 ` [PATCH v2 5/7] hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts Guenter Roeck
2020-01-20 13:58   ` Peter Maydell [this message]
2020-01-20 15:04     ` Guenter Roeck
2020-01-18 16:42 ` [PATCH v2 6/7] hw/char/exynos4210_uart: Add receive DMA support Guenter Roeck
2020-01-18 16:42 ` [PATCH v2 7/7] hw/arm/exynos4210: Connect serial port DMA busy signals with pl330 Guenter Roeck
2020-01-20 13:59   ` Peter Maydell

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