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From: Peter Maydell <peter.maydell@linaro.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Bin Meng" <bin.meng@windriver.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-arm <qemu-arm@nongnu.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>
Subject: Re: [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model
Date: Tue, 2 Feb 2021 11:39:43 +0000	[thread overview]
Message-ID: <CAFEAcA9sDSre3k7YGgwzFBCc22sg2FOuBqVwekQx=fLiFvcevg@mail.gmail.com> (raw)
In-Reply-To: <20210129132323.30946-1-bmeng.cn@gmail.com>

On Fri, 29 Jan 2021 at 13:23, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Starting from v8, the series is based on the following 2 versions:
>
> - v5 series sent from Bin
>   http://patchwork.ozlabs.org/project/qemu-devel/list/?series=223919
> - v7 series sent from Philippe
>   http://patchwork.ozlabs.org/project/qemu-devel/list/?series=224612
>
> This series fixes a bunch of bugs in current implementation of the imx
> spi controller, including the following issues:
>
> - remove imx_spi_update_irq() in imx_spi_reset()
> - chip select signal was not lower down when spi controller is disabled
> - round up the tx burst length to be multiple of 8
> - transfer incorrect data when the burst length is larger than 32 bit
> - spi controller tx and rx fifo endianness is incorrect
> - remove pointless variable (s->burst_length) initialization (Philippe)
> - rework imx_spi_reset() to keep CONREG register value (Philippe)
> - rework imx_spi_read() to handle block disabled (Philippe)
> - rework imx_spi_write() to handle block disabled (Philippe)
>
> Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7
> (interrupt mode).

Applied to target-arm.next, thanks.

-- PMM


      parent reply	other threads:[~2021-02-02 11:41 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-29 13:23 [PATCH v9 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-29 13:23 ` [PATCH v9 01/10] hw/ssi: imx_spi: Use a macro for number of chip selects supported Bin Meng
2021-01-29 13:23 ` [PATCH v9 02/10] hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() Bin Meng
2021-01-29 13:23 ` [PATCH v9 03/10] hw/ssi: imx_spi: Remove pointless variable initialization Bin Meng
2021-01-29 13:23 ` [PATCH v9 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Bin Meng
2021-01-29 14:00   ` Philippe Mathieu-Daudé
2021-01-29 13:23 ` [PATCH v9 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Bin Meng
2021-01-29 13:23 ` [PATCH v9 06/10] hw/ssi: imx_spi: Rework imx_spi_write() " Bin Meng
2021-01-29 13:23 ` [PATCH v9 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Bin Meng
2021-01-29 13:23 ` [PATCH v9 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Bin Meng
2021-01-29 13:23 ` [PATCH v9 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Bin Meng
2021-01-29 13:23 ` [PATCH v9 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness Bin Meng
2021-02-02 11:39 ` Peter Maydell [this message]

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