From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59986) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6JhT-0007b6-83 for qemu-devel@nongnu.org; Mon, 05 Aug 2013 08:15:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6JhN-0006Gp-UP for qemu-devel@nongnu.org; Mon, 05 Aug 2013 08:15:47 -0400 Received: from mail-lb0-f182.google.com ([209.85.217.182]:50965) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6JTj-0000mp-FJ for qemu-devel@nongnu.org; Mon, 05 Aug 2013 08:01:35 -0400 Received: by mail-lb0-f182.google.com with SMTP id v20so1970263lbc.41 for ; Mon, 05 Aug 2013 05:01:34 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <1375701492-21759-1-git-send-email-peter.maydell@linaro.org> <1375701492-21759-3-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Mon, 5 Aug 2013 13:01:14 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v4 2/2] ARM: Add 'virt' platform List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anup Patel Cc: "patches@linaro.org" , qemu-devel@nongnu.org, "kvmarm@lists.cs.columbia.edu" On 5 August 2013 12:48, Anup Patel wrote: >> +static const MemMapEntry a15memmap[] = { >> + [VIRT_FLASH] = { 0, 0x100000 }, > > IMHO, 1 MB of flash is small for possible future expansion. If mach-virt > becomes popular then we can expect people running UBoot or UEFI or > .... from this flash. > > I think having 16 MB of flash would be good because it is multiple of > 2 MB hence we can also create section entries for it in Stage2 TTBL. Seems reasonable. >> + [VIRT_CPUPERIPHS] = { 0x100000, 0x8000 }, > > I would suggest to start peripheral space at 2 MB boundary and also > have its total size in multiple of 2 MB. The total size here is fixed by the CPU hardware -- an A15's private peripheral space is only 0x8000 in size. > This will enable us to create 2 MB > entries in Stage2 TTBL for trapping which in-turn can help in performance > by reducing Stage2 TTBL walks. > > I am sure there won't be too many peripherals in mach-virt so, it would > even better if we can have base address of each peripheral to be at > 2 MB boundary. Why does each individual peripheral have to be at a 2MB boundary? I would expect the kernel to just have a single "nothing mapped" here stage 2 table entry (or entries) covering the whole of the mmio peripheral region regardless of how many devices happen to be inside it. thanks -- PMM