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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 10 Jan 2017 17:17:20 +0000
Message-ID: <CAFEAcA_8p_OBHEYn=Rr9p-e=GFHz3h1kxK8JRSv6oozTzyvQ2g@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v2 04/18] hw/arm/virt: Wire VIRQ, VFIQ,
 maintenance irq lines from GIC to CPU
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To: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>, "patches@linaro.org" <patches@linaro.org>, Andrew Jones <drjones@redhat.com>, Christoffer Dall <christoffer.dall@linaro.org>, Alistair Francis <alistair.francis@xilinx.com>

On 10 January 2017 at 16:42, Edgar E. Iglesias
<edgar.iglesias@xilinx.com> wrote:
> On Mon, Jan 09, 2017 at 04:05:10PM +0000, Peter Maydell wrote:
>> @@ -571,9 +571,17 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
>>                                                     ppibase + timer_irq[irq]));
>>          }
>>
>> +        qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
>> +                                    qdev_get_gpio_in(gicdev, ppibase
>> +                                                     + ARCH_GICV3_MAINT_IRQ));
>> +
>>          sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
>>          sysbus_connect_irq(gicbusdev, i + smp_cpus,
>>                             qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
>> +        sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
>> +                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
>> +        sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
>
> I thought there was an error here first (i.e i * smp_cpus + 3).
> The code is correct but could have perhaps been more readable with named irqs.

Yeah, all the GIC interfacing predates named IRQs and we haven't
got round to trying to convert it (it would be a fairly tedious
job given all the boards that wire up GICs these days).

thanks
-- PMM