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From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 7 Aug 2015 14:50:54 +0100
Message-ID: <CAFEAcA_GcPCu+MAxUm1nyHYyKeYsbaPtVbN7F2Q1kF7nwmFBNw@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v13 16/19] i.MX: Add SOC support for i.MX25
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To: Jean-Christophe Dubois <jcd@tribudubois.net>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Peter Crosthwaite <crosthwaite.peter@gmail.com>

On 16 July 2015 at 22:21, Jean-Christophe Dubois <jcd@tribudubois.net> wrote:
>     For now we support the following devices:
>       * CPU: ARM926
>       * Interrupt Controller: AVIC
>       * CCM
>       * UART x 5
>       * EPIT x 2
>       * GPT x 4
>       * FEC
>       * I2C x 3
>
> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>

> +static void fsl_imx25_realize(DeviceState *dev, Error **errp)
> +{
> +    FslIMX25State *s = FSL_IMX25(dev);
> +    uint8_t i;
> +    Error *err = NULL;
> +
> +    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
> +    if (err) {
> +        error_propagate((errp), (err));

What's with the extra brackets?

> +        return;
> +    }
> +
> +    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
> +    if (err) {
> +        error_propagate((errp), (err));
> +        return;
> +    }
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);

Having SoC realize functions map devices into the system address
space doesn't really seem right to me, but are we already doing this
elsewhere?

> +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
> +                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
> +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
> +                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
> +
> +    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
> +    if (err) {
> +        error_propagate((errp), (err));
> +        return;
> +    }
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
> +
> +    /* Initialize all UARTS */

"UARTs"

thanks
-- PMM