From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bz0ht-0000OY-W1 for qemu-devel@nongnu.org; Tue, 25 Oct 2016 08:19:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bz0hp-0004j3-PZ for qemu-devel@nongnu.org; Tue, 25 Oct 2016 08:19:53 -0400 Received: from mail-ua0-x22c.google.com ([2607:f8b0:400c:c08::22c]:37149) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bz0hp-0004i8-Km for qemu-devel@nongnu.org; Tue, 25 Oct 2016 08:19:49 -0400 Received: by mail-ua0-x22c.google.com with SMTP id b35so12496137uaa.4 for ; Tue, 25 Oct 2016 05:19:49 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1477378140-2670-1-git-send-email-ppandit@redhat.com> References: <1477378140-2670-1-git-send-email-ppandit@redhat.com> From: Peter Maydell Date: Tue, 25 Oct 2016 13:19:28 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH] char: cadence: correct reset value for baud rate registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: P J P Cc: Qemu Developers , qemu-arm , Prasad J Pandit , Alistair Francis , Edgar Iglesias On 25 October 2016 at 07:49, P J P wrote: > From: Prasad J Pandit > > The Cadence UART device emulator stores 'baud rate generator' > and 'baud rate divider' values, used in computing speed, in two > registers. The device specification defines their range and > their reset value. Use their correct value when resetting the > device in cadence_uart_reset. > > Signed-off-by: Prasad J Pandit > --- > hw/char/cadence_uart.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c > index c176446..b8d4c28 100644 > --- a/hw/char/cadence_uart.c > +++ b/hw/char/cadence_uart.c > @@ -471,7 +471,8 @@ static void cadence_uart_reset(DeviceState *dev) > s->r[R_IMR] = 0; > s->r[R_CISR] = 0; > s->r[R_RTRIG] = 0x00000020; > - s->r[R_BRGR] = 0x0000000F; > + s->r[R_BRGR] = 0x0000028B; > + s->r[R_BDIV] = 0x0000000F; > s->r[R_TTRIG] = 0x00000020; > > uart_rx_reset(s); > -- > 2.7.4 I'm going to wait for a review/ack from one of the Xilinx folk before putting this in target-arm.next. thanks -- PMM