From: Peter Maydell <peter.maydell@linaro.org>
To: Vijay Kilari <vijay.kilari@gmail.com>
Cc: qemu-arm <qemu-arm@nongnu.org>,
Christoffer Dall <christoffer.dall@linaro.org>,
Eric Auger <eric.auger@redhat.com>,
Pavel Fedin <p.fedin@samsung.com>,
Marc Zyngier <marc.zyngier@arm.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Subject: Re: [Qemu-devel] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
Date: Mon, 20 Feb 2017 09:51:51 +0000 [thread overview]
Message-ID: <CAFEAcA_NbQNzrUUCAS2e5Xso0rg6H3+nzDjTc9i8Tc+GLpXvLw@mail.gmail.com> (raw)
In-Reply-To: <CALicx6tqxXZxBTxYvF55ydBg5CB1to3MsEkhaohucx4EAZcEJA@mail.gmail.com>
On 20 February 2017 at 06:21, Vijay Kilari <vijay.kilari@gmail.com> wrote:
> Hi Peter,
>
> On Fri, Feb 17, 2017 at 7:25 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
[on the guest-visible ICC_SRE_EL1 value]
>> Is there a situation where KVM might allow a value other
>> than 0x7?
>
> In KVM, the SRE_EL1 value is 0x1. During save, value
> read from KVM is 0x1 though we reset to 0x7.
0x1 meanss "System Register Interface enabled, IRQ
bypass enabled, FIQ bypass enabled". This seems
rather a weird setting, because it means "the GICv3
CPU interface functionality is disabled and the GICv3
should signal interrupts via legacy IRQ and FIQ".
Does KVM really support IRQ/FIQ bypass and does Linux
really leave it enabled rather than turning it off
by writing the value to 1?
My expectation was that the KVM GICv3 emulation would
make these bits RAO/WI like the TCG implementation.
Is there maybe a bug in the kernel side where it
doesn't implement bypass but has made these bits be
RAZ/WI rather than RAO/WI ?
thanks
-- PMM
next prev parent reply other threads:[~2017-02-20 9:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-17 6:31 [Qemu-devel] [PATCH v8 0/5] GICv3 live migration support vijay.kilari
2017-02-17 6:31 ` [Qemu-devel] [PATCH v8 1/5] kernel: Add definitions for GICv3 attributes vijay.kilari
2017-02-17 6:31 ` [Qemu-devel] [PATCH v8 2/5] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate vijay.kilari
2017-02-17 8:49 ` Auger Eric
2017-02-17 13:55 ` Peter Maydell
2017-02-20 6:21 ` Vijay Kilari
2017-02-20 9:51 ` Peter Maydell [this message]
2017-02-22 11:56 ` Vijay Kilari
2017-02-22 12:05 ` Peter Maydell
2017-02-22 12:10 ` Marc Zyngier
2017-02-22 12:40 ` Peter Maydell
2017-02-17 6:31 ` [Qemu-devel] [PATCH v8 3/5] hw/intc/arm_gicv3_kvm: Implement get/put functions vijay.kilari
2017-02-24 17:53 ` Auger Eric
2017-02-17 6:31 ` [Qemu-devel] [PATCH v8 4/5] target-arm: Add GICv3CPUState in CPUARMState struct vijay.kilari
2017-02-17 13:36 ` Peter Maydell
2017-02-17 6:31 ` [Qemu-devel] [PATCH v8 5/5] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers vijay.kilari
2017-02-17 13:40 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAFEAcA_NbQNzrUUCAS2e5Xso0rg6H3+nzDjTc9i8Tc+GLpXvLw@mail.gmail.com \
--to=peter.maydell@linaro.org \
--cc=Vijaya.Kumar@cavium.com \
--cc=christoffer.dall@linaro.org \
--cc=eric.auger@redhat.com \
--cc=marc.zyngier@arm.com \
--cc=p.fedin@samsung.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=vijay.kilari@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.