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From: Peter Maydell <peter.maydell@linaro.org>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>
Cc: David Hildenbrand <david@redhat.com>,
	Jason Wang <jasowang@redhat.com>, Li Qiang <liq3ea@gmail.com>,
	Qiuhao Li <Qiuhao.Li@outlook.com>, Peter Xu <peterx@redhat.com>,
	qemu-devel@nongnu.org, Alexander Bulekov <alxndr@bu.edu>,
	qemu-arm@nongnu.org, Gerd Hoffmann <kraxel@redhat.com>,
	Stefan Hajnoczi <stefanha@redhat.com>,
	"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [RFC PATCH v3 3/3] softmmu/physmem: Introduce MemTxAttrs::memory field and MEMTX_BUS_ERROR
Date: Fri, 17 Dec 2021 22:34:29 +0000	[thread overview]
Message-ID: <CAFEAcA_UKFHT=PbwNtyqV4G2Vdw7LVUjUj_X_DZ5Kk6=yF+EBg@mail.gmail.com> (raw)
In-Reply-To: <20211215182421.418374-4-philmd@redhat.com>

On Wed, 15 Dec 2021 at 18:24, Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> Add the 'memory' bit to the memory attributes to restrict bus
> controller accesses to memories.
>
> Introduce flatview_access_allowed() to check bus permission
> before running any bus transaction.
>
> Have read/write accessors return MEMTX_BUS_ERROR if an access is
> restricted.
>
> There is no change for the default case where 'memory' is not set.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  include/exec/memattrs.h |  9 +++++++++
>  softmmu/physmem.c       | 43 +++++++++++++++++++++++++++++++++++++++--
>  2 files changed, 50 insertions(+), 2 deletions(-)
>
> diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
> index 95f2d20d55b..f0063583ee2 100644
> --- a/include/exec/memattrs.h
> +++ b/include/exec/memattrs.h
> @@ -35,6 +35,14 @@ typedef struct MemTxAttrs {
>      unsigned int secure:1;
>      /* Memory access is usermode (unprivileged) */
>      unsigned int user:1;
> +    /*
> +     * Bus interconnect and peripherals can access anything (memories,
> +     * devices) by default. By setting the 'memory' bit, bus transaction
> +     * are restricted to "normal" memories (per the AMBA documentation)
> +     * versus devices. Access to devices will be logged and rejected
> +     * (see MEMTX_BUS_ERROR).
> +     */
> +    unsigned int memory:1;
>      /* Requester ID (for MSI for example) */
>      unsigned int requester_id:16;
>      /* Invert endianness for this page */
> @@ -66,6 +74,7 @@ typedef struct MemTxAttrs {
>  #define MEMTX_OK 0
>  #define MEMTX_ERROR             (1U << 0) /* device returned an error */
>  #define MEMTX_DECODE_ERROR      (1U << 1) /* nothing at that address */
> +#define MEMTX_BUS_ERROR         (1U << 2) /* bus returned an error */

This is kind of odd naming, because MEMTX_DECODE_ERROR already means
"bus/interconnect returned an error" and it generally translates
into what at the OS level gets called a "bus error"...

-- PMM


  parent reply	other threads:[~2021-12-17 22:36 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-15 18:24 [RFC PATCH v3 0/3] physmem: Have flaview API check bus permission from MemTxAttrs argument Philippe Mathieu-Daudé
2021-12-15 18:24 ` [RFC PATCH v3 1/3] hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR Philippe Mathieu-Daudé
2022-01-19 17:34   ` Philippe Mathieu-Daudé via
2022-01-20 10:53     ` Peter Maydell
2021-12-15 18:24 ` [RFC PATCH v3 2/3] softmmu/physmem: Simplify flatview_write and address_space_access_valid Philippe Mathieu-Daudé
2021-12-15 18:24 ` [RFC PATCH v3 3/3] softmmu/physmem: Introduce MemTxAttrs::memory field and MEMTX_BUS_ERROR Philippe Mathieu-Daudé
2021-12-17 19:46   ` Richard Henderson
2021-12-17 22:34   ` Peter Maydell [this message]
2021-12-17 23:18     ` Philippe Mathieu-Daudé
2021-12-18  2:07       ` Richard Henderson
2021-12-18 11:26         ` Philippe Mathieu-Daudé
2022-01-24 16:16   ` Stefan Hajnoczi
2022-01-24 16:30 ` [RFC PATCH v3 0/3] physmem: Have flaview API check bus permission from MemTxAttrs argument Stefan Hajnoczi
2022-01-24 16:50   ` Alexander Bulekov
2022-01-25 11:51     ` Stefan Hajnoczi

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