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Tue, 18 May 2021 05:47:36 -0700 (PDT) MIME-Version: 1.0 References: <20210416235928.1631788-1-richard.henderson@linaro.org> <20210416235928.1631788-12-richard.henderson@linaro.org> In-Reply-To: <20210416235928.1631788-12-richard.henderson@linaro.org> From: Peter Maydell Date: Tue, 18 May 2021 13:47:19 +0100 Message-ID: Subject: Re: [PATCH v1 11/11] target/arm: Enable BFloat16 extensions To: Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, 17 Apr 2021 at 01:05, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/cpu64.c | 3 +++ > target/arm/cpu_tcg.c | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 379f90fab8..db4f48edcf 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -660,6 +660,7 @@ static void aarch64_max_initfn(Object *obj) > t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); > + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); > t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ > t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); > @@ -707,6 +708,7 @@ static void aarch64_max_initfn(Object *obj) > t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); > t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ > t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); > + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); > t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); > t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); > t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); > @@ -730,6 +732,7 @@ static void aarch64_max_initfn(Object *obj) > u = FIELD_DP32(u, ID_ISAR6, FHM, 1); > u = FIELD_DP32(u, ID_ISAR6, SB, 1); > u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); > + u = FIELD_DP32(u, ID_ISAR6, BF16, 1); > u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); > cpu->isar.id_isar6 = u; > > diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c > index 046e476f65..b2463cf109 100644 > --- a/target/arm/cpu_tcg.c > +++ b/target/arm/cpu_tcg.c > @@ -968,6 +968,7 @@ static void arm_max_initfn(Object *obj) > t = FIELD_DP32(t, ID_ISAR6, FHM, 1); > t = FIELD_DP32(t, ID_ISAR6, SB, 1); > t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); > + t = FIELD_DP32(t, ID_ISAR6, BF16, 1); > cpu->isar.id_isar6 = t; > > t = cpu->isar.mvfr1; Same query as with SVE: do we need to clear these in the "!has_vfp" and "!has_neon" handling code in arm_cpu_realizefn() ? thanks -- PMM