From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aVg9Y-0007S7-6X for qemu-devel@nongnu.org; Tue, 16 Feb 2016 08:58:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aVg9X-0006Fu-89 for qemu-devel@nongnu.org; Tue, 16 Feb 2016 08:58:56 -0500 Received: from mail-vk0-x22d.google.com ([2607:f8b0:400c:c05::22d]:35143) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aVg9X-0006Fp-1Q for qemu-devel@nongnu.org; Tue, 16 Feb 2016 08:58:55 -0500 Received: by mail-vk0-x22d.google.com with SMTP id e6so133399442vkh.2 for ; Tue, 16 Feb 2016 05:58:54 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20160210135200.GD32426@codeaurora.org> References: <9a4369604c653bd21eca8509aa8b160d8cda951f.1454720020.git.alistair.francis@xilinx.com> <20160210135200.GD32426@codeaurora.org> From: Peter Maydell Date: Tue, 16 Feb 2016 13:58:35 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aaron Lindsay Cc: QEMU Developers , Peter Crosthwaite , Nathan Rossi , Christopher Covington , Alistair Francis On 10 February 2016 at 13:52, Aaron Lindsay wrote: > On Feb 09 15:11, Alistair Francis wrote: >> On Tue, Feb 9, 2016 at 9:19 AM, Peter Maydell wrote: >> > On 6 February 2016 at 00:55, Alistair Francis >> > wrote: >> >> diff --git a/target-arm/cpu.c b/target-arm/cpu.c >> >> index 7ddbf3d..937f845 100644 >> >> --- a/target-arm/cpu.c >> >> +++ b/target-arm/cpu.c >> >> @@ -1156,6 +1156,8 @@ static void cortex_a15_initfn(Object *obj) >> >> cpu->id_pfr0 = 0x00001131; >> >> cpu->id_pfr1 = 0x00011011; >> >> cpu->id_dfr0 = 0x02010555; >> >> + cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */ >> > >> > These are: >> > SW_INCR # insn architecturally executed, cc pass, software increment >> > INST_RETIRED # insn architecturally executed >> > CPU_CYCLES # cycle >> > >> > However we don't actually implement any of these, so should >> > we be advertising them? >> >> So this part I took directly from Chris's RFC. I'm happy to take it >> out if you would like. > > I think removing the PMCEID0 change makes sense since these patches > don't implement the advertised counters. We have other patches which do > implement them, but they need some more work, so we can make this change > if/when they're actually implemented. I agree, so I propose to take Alistair's v3 series into target-arm.next with the following change: diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1203783..e95b030 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -1156,7 +1156,7 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr0 = 0x00001131; cpu->id_pfr1 = 0x00011011; cpu->id_dfr0 = 0x02010555; - cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */ + cpu->pmceid0 = 0x0000000; cpu->pmceid1 = 0x00000000; cpu->id_afr0 = 0x00000000; cpu->id_mmfr0 = 0x10201105; diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index fc336e1..fa5eda2 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -135,7 +135,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_isar5 = 0x00011121; cpu->id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; - cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */ + cpu->pmceid0 = 0x00000000; cpu->pmceid1 = 0x00000000; cpu->id_aa64isar0 = 0x00011120; cpu->id_aa64mmfr0 = 0x00001124; If anybody disagrees let me know; otherwise this will go into a pullreq later this week. thanks -- PMM