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Mon, 14 Jun 2021 09:05:03 -0700 (PDT) MIME-Version: 1.0 References: <20210608161028.4159582-1-erdnaxe@crans.org> <20210608161028.4159582-2-erdnaxe@crans.org> In-Reply-To: <20210608161028.4159582-2-erdnaxe@crans.org> From: Peter Maydell Date: Mon, 14 Jun 2021 17:04:28 +0100 Message-ID: Subject: Re: [PATCH 1/2] stm32f100: Add the stm32f100 SoC To: Alexandre Iooss Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=peter.maydell@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:STM32F100" , "open list:All patches CC here" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 8 Jun 2021 at 17:10, Alexandre Iooss wrote: > > This SoC is similar to stm32f205 SoC. > This will be used by the STM32VLDISCOVERY to create a machine. > > Signed-off-by: Alexandre Iooss > --- > MAINTAINERS | 6 ++ > hw/arm/Kconfig | 6 ++ > hw/arm/meson.build | 1 + > hw/arm/stm32f100_soc.c | 182 +++++++++++++++++++++++++++++++++ > include/hw/arm/stm32f100_soc.h | 58 +++++++++++ > 5 files changed, 253 insertions(+) > create mode 100644 hw/arm/stm32f100_soc.c > create mode 100644 include/hw/arm/stm32f100_soc.h > + /* Init ARMv7m */ > + armv7m = DEVICE(&s->armv7m); > + qdev_prop_set_uint32(armv7m, "num-irq", 96); Is this definitely right? The STM32F00 datasheet I found thinks it only has 61 external interrupts. Otherwise Reviewed-by: Peter Maydell thanks -- PMM