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Tue, 12 Jan 2021 02:12:35 -0800 (PST) MIME-Version: 1.0 References: <20210108185154.8108-1-leif@nuviainc.com> In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> From: Peter Maydell Date: Tue, 12 Jan 2021 10:12:24 +0000 Message-ID: Subject: Re: [PATCH v3 0/6] target/arm: various changes to cpu.h To: Leif Lindholm Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Desnogues , qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 8 Jan 2021 at 18:51, Leif Lindholm wrote: > > First, fix a typo in ID_AA64PFR1 (SBSS -> SSBS). > > Second, turn clidr in the ARMCPU struct 64-bit, to support all fields defined > by the ARM ARM. > > Third, add field definitions for CLIDR (excepting the Ttype fields, since > I was unsure of prefererred naming - Ttype7-Ttype1?). > > Fourth add all ID_AA64 registers/fields present in ARM DDI 0487F.c, > > Lastly, add all ID_ (aarch32) registers/fields. > > Some of the ID_AA64 fields will be used by some patches Rebecca Cran will be > submitting shortly, and some of those features also exist for aarch32. Applied to target-arm.next, thanks. -- PMM