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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-arm <qemu-arm@nongnu.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"patches@linaro.org" <patches@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up
Date: Sun, 15 Jul 2018 22:14:27 +0100	[thread overview]
Message-ID: <CAFEAcA_d41+M=tu5DTDrB9=6s5qTQnPZau42s4UyfNWFU8AkZQ@mail.gmail.com> (raw)
In-Reply-To: <5c3ec438-2265-94b4-4f35-71a79d838518@twiddle.net>

On 15 July 2018 at 01:37, Richard Henderson <rth@twiddle.net> wrote:
> On 07/13/2018 10:09 AM, Peter Maydell wrote:
>> @@ -939,29 +935,21 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
>>          }
>>          assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
>>      }
>> +    assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
>
> Don't duplicate the assert; just move it.

Yeah, the duplicate is unwanted: I probably ended upit
from a botched conflict resolution at some point in a rebase
when I was moving it around.

> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

thanks
-- PMM

  reply	other threads:[~2018-07-15 21:14 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-13 15:09 [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up Peter Maydell
2018-07-15  0:37 ` Richard Henderson
2018-07-15 21:14   ` Peter Maydell [this message]
2018-07-24 12:26   ` Peter Maydell
2018-07-24 13:29     ` Richard Henderson
2018-07-15  5:01 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé

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