From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F616C433E0 for ; Fri, 1 Jan 2021 12:04:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F1307221E9 for ; Fri, 1 Jan 2021 12:04:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F1307221E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kvJAC-00085z-Ij for qemu-devel@archiver.kernel.org; Fri, 01 Jan 2021 07:04:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kvJ9N-0007fS-Nb for qemu-devel@nongnu.org; Fri, 01 Jan 2021 07:03:21 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]:37635) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kvJ9M-0002VC-1T for qemu-devel@nongnu.org; Fri, 01 Jan 2021 07:03:21 -0500 Received: by mail-ej1-x62b.google.com with SMTP id ga15so27893090ejb.4 for ; Fri, 01 Jan 2021 04:03:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ppveAjEpvQyjxsj/0lwZhLu2sxlDqyE4w/x/BAJMrFM=; b=r1hZR4Rix+60NQSp7hsIhQRgmwtOIMShnl5Xppv0/0QrHJJ6txFX3Ic/jmimUdhAHa Kh7+IL2ai69FWqL8JfMqjwbvHj6myiyqt0zz8SexW/slbnb4L/NBEyRs5hJVV+niNZK9 CsoUY9SqwO+bG7r4eAk0DiwKtfQHr3XTz6zPJiftdWiCv6mNybLr7mfsjrsv7DhFD0hF 2H93+kSxTz+ljXauQFIspK/G5PzxzjJwNTlSvnY5KT4abvCeYY36h0zyf4WXB4GNiDPI WD/4Qi4+SOoUdZpspu88YEMJ68Oj81W5bVBTsSB84l1frf/Zvg47BEKUajPKfnv5jji6 7vbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ppveAjEpvQyjxsj/0lwZhLu2sxlDqyE4w/x/BAJMrFM=; b=lj/tBRUACZcOQ3KchlLvO9gApnl+S6iPSVysolEWWlPHyPugDOPytWFyG3iXbYHp7t M+6XQudjxAjSy4BR7WixvEjD0+Q7UG1f+BkkWBRLK2aeUpw5K+2wvp3CWusk24dI/q5W re54Je81cgKeyxhdHF1bejgEMtdu/CYO1AZahiNukAgFvjTMF5n6G6J9PaaiZ+m0/zB/ MkPCMz+DcSzKiR+uOFjXRAmfgQlPH3wJJ3tbS5zlVqXjPvEE/NhACgreP6y6eTA9656V CXBKjBT3N65njxMeuooHm+3kziNWMC0DYzX65MaEtbNoPnDNcquZzsYT74t+waBxWjf6 Ln1A== X-Gm-Message-State: AOAM532+mRAuaKxLwlh31rLrK004rzF4KBdtQfdeLwPF0ZymuU4VPZGC cE7Oj7TuV9cP4mqJwlDRswZy+FF47T7x7JSYUI7heA== X-Google-Smtp-Source: ABdhPJygPwlX5CfkG+om7m+d70GjeVr+39CSp23Vyeo0WAefWnHJPaT7JSQYBoOMCP6iS5eNLbcGwCBjaCVdwSgDhsI= X-Received: by 2002:a17:906:195a:: with SMTP id b26mr56207378eje.4.1609502598042; Fri, 01 Jan 2021 04:03:18 -0800 (PST) MIME-Version: 1.0 References: <6892fc8ac57283bf7ba27fe89ea9dbdd6a37f988.1609413115.git.balaton@eik.bme.hu> <79681dc2-d689-4518-a83-dead38dd6e8@eik.bme.hu> In-Reply-To: <79681dc2-d689-4518-a83-dead38dd6e8@eik.bme.hu> From: Peter Maydell Date: Fri, 1 Jan 2021 12:03:07 +0000 Message-ID: Subject: Re: [PATCH v2 3/3] sam460ex: Clean up irq mapping To: BALATON Zoltan Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , qemu-ppc , QEMU Developers , Guenter Roeck , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, 31 Dec 2020 at 20:55, BALATON Zoltan wrote: > The SoC is called 460EX (despite having a PPC 440 core not 460 one) but I > think you've looked at the right data sheet and it's just a typo. I also > don't know how the board is wired so I think in this case I prefer > dropping this patch and keeping the current code just for simplicity but > to avoid going through this again maybe we should add a comment saying why > it's working. Can you please suggest a text for such comment pointing to > the relevant part of pci_change_irq_level() you refer to above? I don't > think I understand it enough to document it. How about: /* * All four IRQ[ABCD] pins from all slots are tied to a single board * IRQ, so our mapping function here maps everything to IRQ 0. * The code in pci_change_irq_level() tracks the number of times * the mapped IRQ is asserted and deasserted, so if multiple devices * assert an IRQ at the same time the behaviour is correct. */ ? thanks -- PMM