From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932130AbaFYOG6 (ORCPT ); Wed, 25 Jun 2014 10:06:58 -0400 Received: from mail-la0-f43.google.com ([209.85.215.43]:41566 "EHLO mail-la0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757165AbaFYOGz (ORCPT ); Wed, 25 Jun 2014 10:06:55 -0400 MIME-Version: 1.0 In-Reply-To: <1403688530-23273-4-git-send-email-marc.zyngier@arm.com> References: <1403688530-23273-1-git-send-email-marc.zyngier@arm.com> <1403688530-23273-4-git-send-email-marc.zyngier@arm.com> From: Peter Maydell Date: Wed, 25 Jun 2014 15:06:33 +0100 Message-ID: Subject: Re: [RFC PATCH 3/9] irqchip: GIC: Convert to EOImode == 1 To: Marc Zyngier Cc: "kvmarm@lists.cs.columbia.edu" , arm-mail-list , lkml - Kernel Mailing List , Catalin Marinas , Thomas Gleixner , Will Deacon , Christoffer Dall , Eric Auger Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25 June 2014 10:28, Marc Zyngier wrote: > For this case, the GIC architecture provides EOImode == 1, where: > - A write to the EOI register drops the priority of the interrupt and leaves > it active. Other interrupts at the same priority level can now be taken, > but the active interrupt cannot be taken again > - A write to the DIR marks the interrupt as inactive, meaning it can > now be taken again. > > We only enable this feature when booted in HYP mode. Also, as most device > trees are broken (they report the CPU interface size to be 4kB, while > the GICv2 CPU interface size is 8kB), output a warning if we're booted > in HYP mode, and disable the feature. Does that mean you guarantee not to write to the DEACTIVATE register if not booted in Hyp mode? I ask because QEMU's GIC emulation doesn't emulate that register, so it would be useful to know if this patch means newer kernels are going to fall over under TCG QEMU... (The correct fix, obviously, is to actually implement the QEMU support for split prio-drop and deactivate. Christoffer, you're our GIC emulation expert now, right? :-) ) thanks -- PMM From mboxrd@z Thu Jan 1 00:00:00 1970 From: peter.maydell@linaro.org (Peter Maydell) Date: Wed, 25 Jun 2014 15:06:33 +0100 Subject: [RFC PATCH 3/9] irqchip: GIC: Convert to EOImode == 1 In-Reply-To: <1403688530-23273-4-git-send-email-marc.zyngier@arm.com> References: <1403688530-23273-1-git-send-email-marc.zyngier@arm.com> <1403688530-23273-4-git-send-email-marc.zyngier@arm.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 25 June 2014 10:28, Marc Zyngier wrote: > For this case, the GIC architecture provides EOImode == 1, where: > - A write to the EOI register drops the priority of the interrupt and leaves > it active. Other interrupts at the same priority level can now be taken, > but the active interrupt cannot be taken again > - A write to the DIR marks the interrupt as inactive, meaning it can > now be taken again. > > We only enable this feature when booted in HYP mode. Also, as most device > trees are broken (they report the CPU interface size to be 4kB, while > the GICv2 CPU interface size is 8kB), output a warning if we're booted > in HYP mode, and disable the feature. Does that mean you guarantee not to write to the DEACTIVATE register if not booted in Hyp mode? I ask because QEMU's GIC emulation doesn't emulate that register, so it would be useful to know if this patch means newer kernels are going to fall over under TCG QEMU... (The correct fix, obviously, is to actually implement the QEMU support for split prio-drop and deactivate. Christoffer, you're our GIC emulation expert now, right? :-) ) thanks -- PMM