From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 563A0C4338F for ; Thu, 19 Aug 2021 19:25:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0CA276108D for ; Thu, 19 Aug 2021 19:25:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0CA276108D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:38792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGnfd-0004Ht-7c for qemu-devel@archiver.kernel.org; Thu, 19 Aug 2021 15:25:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGner-0003Uk-Oe for qemu-devel@nongnu.org; Thu, 19 Aug 2021 15:24:57 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:40726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGnen-0007Xc-Ni for qemu-devel@nongnu.org; Thu, 19 Aug 2021 15:24:57 -0400 Received: by mail-ej1-x62c.google.com with SMTP id lo4so15011056ejb.7 for ; Thu, 19 Aug 2021 12:24:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1S5rlGQJOxW6i/Vbiv/03PIWeJgR2rqloSYKR9ehRAI=; b=OaSGn28otDNUeIrTkqb1t++fsibOp06830IQfZ6HLdRnd60B4du444HlXmChx6j0PI NzpU0bfQJcSBslz2Eg2UR+5/6xLWUBUdTFbBvWBqwNGwrzwjkyjKpnqsiBPwrjtg7qUC php8OkiKXID4e4NfAgc7afhwOtCtZoQ6He+sOmp+kv4eETRWvzuuGXzeee11d2Q6wJbl aVaq0yVvjyWL4m4Twvug1x/c2Lt/RwQQFU0LzBKhK5ErKHwNkcMMy6oeFpDgPFXDniU1 MOmjPTaQyndoaZzK00Mg/+XvCA5zJgBnGZpt8FCWqWPz7bKQemjoxNfbr7fz/e5aew4R NEEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1S5rlGQJOxW6i/Vbiv/03PIWeJgR2rqloSYKR9ehRAI=; b=Wf4cODQwdsAZDBcsbww/S2xKn5BrPLZLZoJOKytco630049OEXds/t1B3bucd3088D jxob4316dRC+/bm9ZPBqTYEP4YFCCnSf5qtZIfUrAZ4mNq9zlcJiTIYar70RvLOEdGFf 5vO3h83rXuV//F61Mi60xBQ8WS6n4bL7zgroMN0kI6i4WsmGKdO2OKl6UCmtninx0+5i XGi2dNJSkTBqF3Lr8QNVuWIc0oVeXOQsJC7Sv5OfvTsNUPX1grHqnqOiuHLRY1hX+FlV tfTUKEy2eGU9OhffWje8dAZQB3EmUaN+68f1wTkKg9YI8vrMevn0xiGzCZ/KTBjrl4ZR k+4g== X-Gm-Message-State: AOAM530e5lpY7EMj8gGC6QhUlahMcOgbdXpGe9iJT4ZZjC3lTegVo2b/ bBW9jHbAwmRSGJCy3kQCRKDwpG4DAbjtKks9bDKF1g== X-Google-Smtp-Source: ABdhPJyZvE9XL+8yzhFhf2VJ5VZR9d3PJdopOJhjfb5/8+fGrovd/dDVwjht5IIosen+i4tOOmsKgbEk800JuRLVMHI= X-Received: by 2002:a17:906:3bc3:: with SMTP id v3mr17289627ejf.482.1629401092304; Thu, 19 Aug 2021 12:24:52 -0700 (PDT) MIME-Version: 1.0 References: <20210818010041.337010-1-richard.henderson@linaro.org> <20210818010041.337010-4-richard.henderson@linaro.org> In-Reply-To: From: Peter Maydell Date: Thu, 19 Aug 2021 20:24:06 +0100 Message-ID: Subject: Re: [PATCH 3/4] target/arm: Take an exception if PC is misaligned To: Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, 19 Aug 2021 at 17:57, Richard Henderson wrote: > > On 8/19/21 6:50 AM, Richard Henderson wrote: > > On 8/19/21 3:40 AM, Peter Maydell wrote: > >>> uint32_t insn; > >>> bool is_16bit; > >>> > >>> - if (arm_pre_translate_insn(dc)) { > >>> + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { > >> > >> > >> Is it not possible to get a misaligned PC in the Thumb case ? > > > > No. The thumb bit is always removed, leaving all pc aligned mod 2. > > Both BXWritePC and BranchWritePC do this, as do we in gen_bx and store_reg. > > Do you think it's worth an assert here to make sure we never miss a case? I did an audit > of the exception code and it looks like we mask everything correctly there, but... (Did you check the M-profile code too? That also architecturally I think should never let PC have the low bit set; hopefully the code I wrote actually ensures that...) I guess an assert() is more helpful than ploughing ahead with a misaligned PC value. If we don't assert we should at least have a comment saying misaligned Thumb PCs are architecturally impossible. If we do go for the assert, then the comment in arm_cpu_gdb_write_register() about why we don't let GDB set bit 0 in the PC would need updating (there would now be two reasons). We should probably also fail the migration if we get an unaligned Thumb PC in the inbound data. -- PMM