From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:35368)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1XXXNk-0006p9-BQ
	for qemu-devel@nongnu.org; Fri, 26 Sep 2014 11:24:32 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1XXXNd-0000AG-JF
	for qemu-devel@nongnu.org; Fri, 26 Sep 2014 11:24:28 -0400
Received: from mail-pd0-f172.google.com ([209.85.192.172]:59168)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <peter.maydell@linaro.org>) id 1XXXNd-00007r-Ee
	for qemu-devel@nongnu.org; Fri, 26 Sep 2014 11:24:21 -0400
Received: by mail-pd0-f172.google.com with SMTP id g10so1198209pdj.31
	for <qemu-devel@nongnu.org>; Fri, 26 Sep 2014 08:24:15 -0700 (PDT)
MIME-Version: 1.0
In-Reply-To: <1411718914-6608-1-git-send-email-edgar.iglesias@gmail.com>
References: <1411718914-6608-1-git-send-email-edgar.iglesias@gmail.com>
From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 26 Sep 2014 16:23:54 +0100
Message-ID: <CAFEAcA_qBZ6PjnqkYAqa=zOS3sfWdPaNyU70fEMaSxz=5vDXVw@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64
	EL2/3 exception model
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Rob Herring <rob.herring@linaro.org>, Peter Crosthwaite <peter.crosthwaite@xilinx.com>, Fabian Aggeler <aggelerf@ethz.ch>, Sergey Fedorov <serge.fdrv@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>, Alexander Graf <agraf@suse.de>, Greg Bellows <greg.bellows@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, Christoffer Dall <christoffer.dall@linaro.org>, Richard Henderson <rth@twiddle.net>

On 26 September 2014 09:08, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Hi,
>
> This is a second round of AArch64 EL2/3 patches working on the exception
> model. Among other things adding HVC/SMC, interrupt routing to EL2/3 and
> Virtual IRQs/FIQs. The VIRQ/VFIQ support only adds the external signal
> delivery method.
>
> This conflicts slightly with the PSCI emulation patches that Rob posted.
> A rebase should be trivial, hooking in the PSCI emulation calls in the
> HVC/SMC code.

Thanks. I've applied these to target-arm.next, with
some minor fixups to account for the cpu-exec
refactoring. Pushed to my git repo if you want
to grab it before I get round to doing a pullreq:
git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next

(I would still have preferred if we'd just implemented
the interrupt routing right to start with but in
the interests of making progress I'll let that pass.)

-- PMM