From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VzRxa-0007C0-Fu for qemu-devel@nongnu.org; Sat, 04 Jan 2014 09:12:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VzRxT-0002F0-8m for qemu-devel@nongnu.org; Sat, 04 Jan 2014 09:12:18 -0500 Received: from mail-lb0-f179.google.com ([209.85.217.179]:46023) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VzRxT-0002Eo-20 for qemu-devel@nongnu.org; Sat, 04 Jan 2014 09:12:11 -0500 Received: by mail-lb0-f179.google.com with SMTP id w7so8734574lbi.38 for ; Sat, 04 Jan 2014 06:12:10 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <1387752607-23755-1-git-send-email-peter.maydell@linaro.org> <1387752607-23755-16-git-send-email-peter.maydell@linaro.org> From: Peter Maydell Date: Sat, 4 Jan 2014 14:11:50 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement minimal set of EL0-visible sysregs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: Laurent Desnogues , Patch Tracking , Michael Matz , Alexander Graf , "qemu-devel@nongnu.org Developers" , Claudio Fontana , Dirk Mueller , Will Newton , =?UTF-8?B?QWxleCBCZW5uw6ll?= , "kvmarm@lists.cs.columbia.edu" , Christoffer Dall , Richard Henderson On 4 January 2014 13:32, Peter Crosthwaite wrote: > On Mon, Dec 23, 2013 at 8:49 AM, Peter Maydell wrote: >> +static const ARMCPRegInfo v8_cp_reginfo[] = { >> + /* Minimal set of EL0-visible registers. This will need to be expanded >> + * significantly for system emulation of AArch64 CPUs. >> + */ >> + { .name = "NZCV", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, >> + .access = PL0_RW, .type = ARM_CP_NZCV }, >> + {. name = "FPCR", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, >> + .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, >> + {. name = "FPSR", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, >> + .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, >> + /* This claims a 32 byte cacheline size for icache and dcache, VIPT icache. >> + * It will eventually need to have a CPU-specified reset value. >> + */ > > Not sure why this can't be solved short term as there is already the > ctr field in cpu state struct as used by 32. I hadn't noticed that the register was aliased to the CTR AArch32 register. NB that we can't just share a single reginfo for AArch64 and AArch32 though -- the permissions are different since in AArch32 this is accessible only in EL1 and above. My aim here was mostly to set out a framework for how the system register integration will work with system emulation, but just to provide low-effort implementations of the EL0-visible regs for the initial user-emulation patchset. (In the SuSE patchset these are actually just all implemented as special cases inline in translate-a64.c, so to some extent this array is just those special cases converted over to reginfo.) thanks -- PMM