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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 5 Jun 2018 18:27:24 +0100
Message-ID: <CAFEAcA_x8ojrswLGUwJ7iJ1voQf1Mr7qexv0NvnYRdfkanAUeA@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v3b 14/18] target/arm: Implement SVE
 Predicate Count Group
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, qemu-arm <qemu-arm@nongnu.org>

On 30 May 2018 at 19:01, Richard Henderson <richard.henderson@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper-sve.h    |   2 +
>  target/arm/sve_helper.c    |  14 ++++
>  target/arm/translate-sve.c | 132 +++++++++++++++++++++++++++++++++++++
>  target/arm/sve.decode      |  27 ++++++++
>  4 files changed, 175 insertions(+)

> +/*
> + *** SVE Predicate Count Group
> + */
> +
> +static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg)
> +{
> +    unsigned psz = pred_full_reg_size(s);
> +
> +    if (psz <= 8) {
> +        uint64_t psz_mask;
> +
> +        tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn));
> +        if (pn != pg) {
> +            TCGv_i64 g = tcg_temp_new_i64();
> +            tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg));
> +            tcg_gen_and_i64(val, val, g);
> +            tcg_temp_free_i64(g);
> +        }
> +
> +        /* Reduce the pred_esz_masks value simply to reduce the
> +           size of the code generated here.  */
> +        psz_mask = deposit64(0, 0, psz * 8, -1);

isn't this just psz_mask = MAKE_64BIT_MASK(0, psz * 8); ?

> +        tcg_gen_andi_i64(val, val, pred_esz_masks[esz] & psz_mask);
> +
> +        tcg_gen_ctpop_i64(val, val);
> +    } else {

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM