From: Peter Maydell <peter.maydell@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Damien Hedde <damien.hedde@greensocs.com>,
"Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
Mauro Matteo Cascella <mcascell@redhat.com>,
Gaoning Pan <gaoning.pgn@antgroup.com>,
Alistair Francis <alistair@alistair23.me>,
QEMU Developers <qemu-devel@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Gaoning Pan <pgn@zju.edu.cn>
Subject: Re: [RFC PATCH] hw/misc/zynq_slcr: Avoid #DIV/0! error
Date: Tue, 15 Dec 2020 13:37:14 +0000 [thread overview]
Message-ID: <CAFEAcA_zcbw-8G0dOiRAAv-bsPV_M3_E-x3mtcLgkvDjYEEfSQ@mail.gmail.com> (raw)
In-Reply-To: <20201210141610.884600-1-f4bug@amsat.org>
On Thu, 10 Dec 2020 at 14:16, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Malicious user can set the feedback divisor for the PLLs
> to zero, triggering a floating-point exception (SIGFPE).
>
> As the datasheet [*] is not clear how hardware behaves
> when these bits are zeroes, use the maximum divisor
> possible (128) to avoid the software FPE.
>
> [*] Zynq-7000 TRM, UG585 (v1.12.2)
> B.28 System Level Control Registers (slcr)
> -> "Register (slcr) ARM_PLL_CTRL"
> 25.10.4 PLLs
> -> "Software-Controlled PLL Update"
>
> Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts")
> Reported-by: Gaoning Pan <pgn@zju.edu.cn>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2020-12-15 13:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-10 14:16 [RFC PATCH] hw/misc/zynq_slcr: Avoid #DIV/0! error Philippe Mathieu-Daudé
2020-12-10 16:39 ` Alistair Francis
2020-12-10 20:13 ` Edgar E. Iglesias
2020-12-11 15:26 ` Damien Hedde
2020-12-10 17:21 ` Mauro Matteo Cascella
2020-12-15 13:37 ` Peter Maydell [this message]
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