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d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NrLeJeQW4CwM4YYqh/9HBl4fcZTaI1H7o8r7JFcqhWQ=; b=rjqwOL7IWZkXjJ10wkkBD+3TxrnZJng0p63E0ElsNZ447NYfq5952MvF/c4rcmHZjl TPWAK9eNRWhBQvR4Phn6qLk8N0oQwWUBxHJA5v5JjTgmdoApJ0btLsnH4AtUWHeet0/s dyJ84MXqcuylFefYZt88teGRDCSYaXsTJAXcW9/gRmqUyjJXCznrlnfmCgo5kc8lzxsi 7UGvJ90jnAEZCrV61F357jFR+2YQG3+LSUqbHIncBFMXIw3wZnvStAqWRWUid+TRD5nU QmkMMwlQUyLWca4JNYJsBRdhyDbe16JZC3SmQjhwTb49ok1/68LlEIU5eAz6XLfgyqyd GcMA== X-Gm-Message-State: ACrzQf0PxOivBah4ikPdZrw8gbe31iyTZO8ajh2Y/tZ0GJ9dhY9pRCql yWccH9jbYpS3GvDJtva3MLFBoQJMrunlmSPhlPI= X-Google-Smtp-Source: AMsMyM46ItaMW/YbRKHOWYGL4yqHV5SVV41g2g/r7d1XwAYTdcjHlLEE4HhNvEmfRZCxIXu3a0ZdjYzbfU+pA05RDNA= X-Received: by 2002:a17:907:3f13:b0:799:6aef:9837 with SMTP id hq19-20020a1709073f1300b007996aef9837mr25869001ejc.296.1667420989714; Wed, 02 Nov 2022 13:29:49 -0700 (PDT) MIME-Version: 1.0 References: <20220922033116.915635-1-judge.packham@gmail.com> <20220922033116.915635-6-judge.packham@gmail.com> <71693582-9fb7-6f2f-d7d3-47376d5ecbbf@denx.de> In-Reply-To: <71693582-9fb7-6f2f-d7d3-47376d5ecbbf@denx.de> From: Chris Packham Date: Thu, 3 Nov 2022 09:29:36 +1300 Message-ID: Subject: Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board To: Stefan Roese Cc: Elad Nachman , Vadym Kochan , Andre Przywara , Chris Packham , Christian Hewitt , Fabio Estevam , Marcel Ziswiler , Marek Vasut , =?UTF-8?Q?Pali_Roh=C3=A1r?= , Samuel Holland , Simon Glass , Tom Rini , "Ying-Chun Liu (PaulLiu)" , u-boot@lists.denx.de Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Thu, Nov 3, 2022 at 2:40 AM Stefan Roese wrote: > > Hi Chris, > > On 22.09.22 05:31, Chris Packham wrote: > > The RD-AC5X-32G16HVG6HLG-A0 development board main components and > > features include: > > * Main 12V/54V power supply > > * 270 Gbps throughput packet processor on the main board > > * DDR4: > > * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs) > > * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs) > > * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement > > * 16GB eMMC (Samsung KLMAG1JETD-B041006) > > * 16MB SPI NOR(GD25Q127C) > > * 32 x 1000 Base-T interfaces > > * 16 x 2500 Base-T interfaces > > * SR1: 88E2540*4 > > * SR2: 88E2580*1+88E2540*2 > > * Six (6) x 25G Base-R SFP28 interfaces > > * One (1) x RJ-45 console connector, interfacing to the on board UART > > * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0) > > * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port = (1) > > * One (1) x RJ-45 1G Base-T Management port, interfacing to the host > > port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy > > * One (1) x Oculink port, interfacing to the PCIe port for external CPU > > connection > > * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~ > > Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881 > > solution) > > * POE total power budget 780W > > * LED interfaces per network port/POE > > * LED interfaces (common) showing system status > > * PTP TC mode Supported (Reserved M.2 connector to support BC mode) > > > > Signed-off-by: Chris Packham > > --- > > > > Changes in v4: > > - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to > > the defconfig. > > - Remove CONFIG_BAUDRATE as this is already set in the default config > > - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with > > DM_USB > > - Remove CONFIG_PREBOOT as we don't have anything to run > > - Remove commented out CONFIG_BOARD_EARLY_INIT_R > > - Remove DEBUG_UART configuration > > - Remove unnecessary console environment variable > > - Remove CONFIG_MVEBU_SAR > > > > Changes in v3: > > - Remove MMC and UBIFS distroboot options (MMC driver is not currently > > functional, NAND is not populated on the RD-AC5X board) > > - Remove unnecessary Ethernet configuration > > - Remove unnecessary NAND configuration > > - Remove memory node from dts so the value passed by the DDR FW will be > > used > > > > Changes in v2: > > - Use distro boot by default > > - remove unnecessary SPI-NOR partitions > > > > arch/arm/dts/Makefile | 3 +- > > arch/arm/dts/ac5-98dx35xx-rd.dts | 129 ++++++++++++++++++++= + > > arch/arm/mach-mvebu/Kconfig | 9 +- > > board/Marvell/mvebu_alleycat-5/MAINTAINERS | 6 + > > board/Marvell/mvebu_alleycat-5/Makefile | 3 + > > board/Marvell/mvebu_alleycat-5/board.c | 28 +++++ > > configs/mvebu_ac5_rd_defconfig | 84 ++++++++++++++ > > include/configs/mvebu_alleycat-5.h | 42 +++++++ > > 8 files changed, 302 insertions(+), 2 deletions(-) > > create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts > > create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS > > create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile > > create mode 100644 board/Marvell/mvebu_alleycat-5/board.c > > create mode 100644 configs/mvebu_ac5_rd_defconfig > > create mode 100644 include/configs/mvebu_alleycat-5.h > > While running a CI build I run into these issues: > > CONFIG_SYS_TEXT_BASE is now renamed to CONFIG_TEXT_BASE. I've already > fixes this locally. But now I also get this compilation error: > > [stefan@ryzen u-boot-marvell (master)]$ make -sj > > Device Tree Source (arch/arm/dts/unset.dtb) is not correctly specified. > Please define 'CONFIG_DEFAULT_DEVICE_TREE' > or build with 'DEVICE_TREE=3D' argument > > make[1]: *** [dts/Makefile:34: arch/arm/dts/unset.dtb] Error 1 > make: *** [Makefile:1162: dts/dt.dtb] Error 2 > > So where is CONFIG_DEFAULT_DEVICE_TREE defined? I might have overlooked > this. > Ah. Because these arm64 SoCs need other components in the "bootloader" I've been using a meta build system that passes DEVICE_TREE=3D on the make command line. I'll rebase the series and add fixup CONFIG_TEXT_BASE/CONFIG_DEFAULT_DEVICE_TREE. > Thanks, > Stefan > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 965895bc2a..57a5272884 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=3D = \ > > cn9132-db-A.dtb \ > > cn9132-db-B.dtb \ > > cn9130-crb-A.dtb \ > > - cn9130-crb-B.dtb > > + cn9130-crb-B.dtb \ > > + ac5-98dx35xx-rd.dtb > > endif > > > > dtb-$(CONFIG_ARCH_SYNQUACER) +=3D synquacer-sc2a11-developerbox.dtb > > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35= xx-rd.dts > > new file mode 100644 > > index 0000000000..d9f217cd4a > > --- /dev/null > > +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts > > @@ -0,0 +1,129 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Device Tree For RD-AC5X. > > + * > > + * Copyright (C) 2021 Marvell > > + * Copyright (C) 2022 Allied Telesis Labs > > + */ > > +/* > > + * Device Tree file for Marvell Alleycat 5X development board > > + * This board file supports the B configuration of the board > > + */ > > + > > +/dts-v1/; > > + > > +#include "ac5-98dx35xx.dtsi" > > + > > +/ { > > + model =3D "Marvell RD-AC5X Board"; > > + compatible =3D "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; > > + > > + aliases { > > + serial0 =3D &uart0; > > + spiflash0 =3D &spiflash0; > > + gpio0 =3D &gpio0; > > + gpio1 =3D &gpio1; > > + ethernet0 =3D ð0; > > + ethernet1 =3D ð1; > > + spi0 =3D &spi0; > > + i2c0 =3D &i2c0; > > + i2c1 =3D &i2c1; > > + usb0 =3D &usb0; > > + usb1 =3D &usb1; > > + pinctrl0 =3D &pinctrl0; > > + sar-reg0 =3D "/config-space/sar-reg"; > > + }; > > + > > + usb1phy: usb-phy { > > + compatible =3D "usb-nop-xceiv"; > > + #phy-cells =3D <0>; > > + }; > > + > > + chosen { > > + stdout-path =3D "serial0:115200n8"; > > + }; > > +}; > > + > > +&uart0 { > > + status =3D "okay"; > > +}; > > + > > +&mdio { > > + phy0: ethernet-phy@0 { > > + reg =3D <0>; > > + }; > > +}; > > + > > +&i2c0 { > > + status =3D "okay"; > > +}; > > + > > +&i2c1 { > > + status =3D "okay"; > > +}; > > + > > +ð0 { > > + status =3D "okay"; > > + phy-handle =3D <&phy0>; > > +}; > > + > > +/* USB0 is a host USB */ > > +&usb0 { > > + status =3D "okay"; > > +}; > > + > > +/* USB1 is a peripheral USB */ > > +&usb1 { > > + status =3D "okay"; > > + phys =3D <&usb1phy>; > > + phy-names =3D "usb-phy"; > > + dr_mode =3D "peripheral"; > > +}; > > + > > +&spi0 { > > + status =3D "okay"; > > + > > + spiflash0: flash@0 { > > + compatible =3D "jedec,spi-nor"; > > + spi-max-frequency =3D <50000000>; > > + spi-tx-bus-width =3D <1>; /* 1-single, 2-dual, 4-quad */ > > + spi-rx-bus-width =3D <1>; /* 1-single, 2-dual, 4-quad */ > > + reg =3D <0>; > > + > > + #address-cells =3D <1>; > > + #size-cells =3D <1>; > > + }; > > +}; > > + > > +&pinctrl0 { > > + /* > > + * MPP Bus: MPP# mode# > > + * eMMC [0-11] 0x1 > > + * SPI[0] [12-17] 0x1 > > + * TSEN_INT [18] 0x1 > > + * DEV_INIT [19] 0x1 > > + * SPI[1] [20-23] 0x3 > > + * UART[1] [24-25] 0x3 > > + * I2C[0] [26-27] 0x1 > > + * XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to = CPSS problem > > + * SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to= CPSS problem > > + * UART[0] [32-33] 0x1 > > + * OOB_SMI [34-35] 0x1 > > + * PTP_CLK0_OUT [36] 0x1 > > + * PTP_PULSE_OUT [37] 0x1 > > + * RCVR_CLK_OUT [38] 0x1 > > + * GPIO(in/out) [39] 0x0 > > + * GPIO(in/out) [40] 0x0 > > + * PTP_REF_CLK [41] 0x1 > > + * PTP_CLK0 [42] 0x1 > > + * LED0_CLK [43] 0x1 > > + * LED0_STB [44] 0x1 > > + * LED0_DATA [45] 0x1 > > + */ > > + /* 0 1 2 3 4 5 6 7 8 9 */ > > + pin-func =3D < 1 1 1 1 1 1 1 1 1 1 > > + 1 1 1 1 1 1 1 1 1 1 > > + 3 3 3 3 3 3 1 1 1 1 > > + 2 2 1 1 1 1 1 1 1 0 > > + 0 1 1 1 1 1 >; > > +}; > > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig > > index 45efa24194..2120cb473f 100644 > > --- a/arch/arm/mach-mvebu/Kconfig > > +++ b/arch/arm/mach-mvebu/Kconfig > > @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT > > bool > > > > choice > > - prompt "Armada XP/375/38x/3700/7K/8K board select" > > + prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select" > > optional > > > > config TARGET_CLEARFOG > > @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K > > select BOARD_LATE_INIT > > imply SCSI > > > > +config TARGET_MVEBU_ALLEYCAT5 > > + bool "Support AlleyCat 5 platforms" > > + select ALLEYCAT_5 > > + > > config TARGET_OCTEONTX2_CN913x > > bool "Support CN913x platforms" > > select ARMADA_8K > > @@ -257,6 +261,7 @@ config SYS_BOARD > > default "x530" if TARGET_X530 > > default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG > > default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 > > + default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 > > > > config SYS_CONFIG_NAME > > default "clearfog" if TARGET_CLEARFOG > > @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME > > default "x530" if TARGET_X530 > > default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG > > default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 > > + default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 > > > > config SYS_VENDOR > > default "Marvell" if TARGET_DB_MV784MP_GP > > @@ -296,6 +302,7 @@ config SYS_VENDOR > > default "gdsys" if TARGET_CONTROLCENTERDC > > default "alliedtelesis" if TARGET_X530 > > default "mikrotik" if TARGET_CRS3XX_98DX3236 > > + default "Marvell" if TARGET_MVEBU_ALLEYCAT5 > > > > config SYS_SOC > > default "mvebu" > > diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell= /mvebu_alleycat-5/MAINTAINERS > > new file mode 100644 > > index 0000000000..480c07c5f0 > > --- /dev/null > > +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS > > @@ -0,0 +1,6 @@ > > +RD-AC5X BOARD > > +M: Chris Packham > > +S: Maintained > > +F: board/Marvell/mvebu_alleycat-5/ > > +F: include/configs/mvebu_alleycat-5.h > > +F: configs/mvebu_ac5_rd_defconfig > > diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mv= ebu_alleycat-5/Makefile > > new file mode 100644 > > index 0000000000..29254b4d64 > > --- /dev/null > > +++ b/board/Marvell/mvebu_alleycat-5/Makefile > > @@ -0,0 +1,3 @@ > > +# SPDX-License-Identifier: GPL-2.0+ > > + > > +obj-y :=3D board.o > > diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mve= bu_alleycat-5/board.c > > new file mode 100644 > > index 0000000000..2d46775920 > > --- /dev/null > > +++ b/board/Marvell/mvebu_alleycat-5/board.c > > @@ -0,0 +1,28 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > + > > +#include > > +#include > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +int board_early_init_f(void) > > +{ > > + return 0; > > +} > > + > > +int board_early_init_r(void) > > +{ > > + return 0; > > +} > > + > > +int board_init(void) > > +{ > > + gd->bd->bi_boot_params =3D CONFIG_SYS_SDRAM_BASE + 0x100; > > + > > + return 0; > > +} > > + > > +int board_late_init(void) > > +{ > > + return 0; > > +} > > diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defc= onfig > > new file mode 100644 > > index 0000000000..610d628705 > > --- /dev/null > > +++ b/configs/mvebu_ac5_rd_defconfig > > @@ -0,0 +1,84 @@ > > +CONFIG_ARM=3Dy > > +CONFIG_ARCH_CPU_INIT=3Dy > > +CONFIG_ARCH_MVEBU=3Dy > > +CONFIG_SYS_TEXT_BASE=3D0x200000000 > > +CONFIG_SYS_MALLOC_LEN=3D0x900000 > > +CONFIG_TARGET_MVEBU_ALLEYCAT5=3Dy > > +CONFIG_ENV_SIZE=3D0x10000 > > +CONFIG_ENV_OFFSET=3D0x400000 > > +CONFIG_ENV_SECT_SIZE=3D0x10000 > > +CONFIG_DM_GPIO=3Dy > > +CONFIG_SYS_LOAD_ADDR=3D0x202000000 > > +CONFIG_SYS_MEMTEST_START=3D0x200800000 > > +CONFIG_SYS_MEMTEST_END=3D0x200ffffff > > +CONFIG_DISTRO_DEFAULTS=3Dy > > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=3Dy > > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=3D0x200FF0000 > > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > > +CONFIG_FIT=3Dy > > +CONFIG_BOOTDELAY=3D-1 > > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=3Dy > > +CONFIG_SYS_CONSOLE_INFO_QUIET=3Dy > > +CONFIG_DISPLAY_BOARDINFO_LATE=3Dy > > +CONFIG_ARCH_EARLY_INIT_R=3Dy > > +CONFIG_ARCH_MISC_INIT=3Dy > > +CONFIG_BOARD_EARLY_INIT_F=3Dy > > +CONFIG_CMD_BOOTZ=3Dy > > +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=3D10 > > +CONFIG_CMD_MEMTEST=3Dy > > +# CONFIG_CMD_FLASH is not set > > +CONFIG_CMD_GPIO=3Dy > > +CONFIG_CMD_I2C=3Dy > > +CONFIG_CMD_MMC=3Dy > > +CONFIG_CMD_PCI=3Dy > > +CONFIG_CMD_SPI=3Dy > > +CONFIG_CMD_USB=3Dy > > +# CONFIG_CMD_SETEXPR is not set > > +CONFIG_CMD_CACHE=3Dy > > +CONFIG_CMD_TIME=3Dy > > +CONFIG_CMD_MVEBU_BUBT=3Dy > > +CONFIG_CMD_REGULATOR=3Dy > > +CONFIG_CMD_EXT4_WRITE=3Dy > > +CONFIG_CMD_UBI=3Dy > > +CONFIG_MAC_PARTITION=3Dy > > +CONFIG_OF_EMBED=3Dy > > +CONFIG_ENV_OVERWRITE=3Dy > > +CONFIG_ENV_IS_IN_SPI_FLASH=3Dy > > +CONFIG_CLK=3Dy > > +CONFIG_CLK_MVEBU=3Dy > > +CONFIG_DM_PCA953X=3Dy > > +CONFIG_DM_I2C=3Dy > > +CONFIG_SYS_I2C_MVTWSI=3Dy > > +CONFIG_MISC=3Dy > > +CONFIG_MMC_SDHCI=3Dy > > +CONFIG_MMC_SDHCI_XENON=3Dy > > +CONFIG_MTD=3Dy > > +CONFIG_SPI_FLASH_GIGADEVICE=3Dy > > +CONFIG_SPI_FLASH_MACRONIX=3Dy > > +CONFIG_SPI_FLASH_SPANSION=3Dy > > +CONFIG_SPI_FLASH_STMICRO=3Dy > > +CONFIG_PHY_MARVELL=3Dy > > +CONFIG_PHY_GIGE=3Dy > > +CONFIG_E1000=3Dy > > +CONFIG_MVNETA=3Dy > > +CONFIG_MVMDIO=3Dy > > +CONFIG_PCI=3Dy > > +CONFIG_PHY=3Dy > > +CONFIG_PINCTRL=3Dy > > +CONFIG_PINCTRL_ARMADA_8K=3Dy > > +CONFIG_DM_REGULATOR_FIXED=3Dy > > +CONFIG_DM_REGULATOR_GPIO=3Dy > > +CONFIG_DM_RTC=3Dy > > +CONFIG_DM_SCSI=3Dy > > +CONFIG_SYS_NS16550=3Dy > > +CONFIG_MVEBU_A3700_SPI=3Dy > > +CONFIG_DM_THERMAL=3Dy > > +CONFIG_USB=3Dy > > +CONFIG_USB_XHCI_HCD=3Dy > > +CONFIG_USB_EHCI_HCD=3Dy > > +CONFIG_USB_HOST_ETHER=3Dy > > +CONFIG_USB_ETHER_ASIX=3Dy > > +CONFIG_USB_ETHER_ASIX88179=3Dy > > +CONFIG_USB_ETHER_MCS7830=3Dy > > +CONFIG_USB_ETHER_RTL8152=3Dy > > +CONFIG_USB_ETHER_SMSC95XX=3Dy > > diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu= _alleycat-5.h > > new file mode 100644 > > index 0000000000..41bdfae6c3 > > --- /dev/null > > +++ b/include/configs/mvebu_alleycat-5.h > > @@ -0,0 +1,42 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * Copyright (C) 2018 Marvell International Ltd > > + */ > > + > > +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H > > +#define _CONFIG_MVEBU_ALLEYCAY_5_H > > + > > +#include > > + > > +/* additions for new ARM relocation support */ > > +#define CONFIG_SYS_SDRAM_BASE 0x200000000 > > + > > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ > > + 115200, 230400, 460800, 921600 } > > + > > +/* Default Env vars */ > > +#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error = */ > > +#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error = */ > > +#define CONFIG_NETMASK 255.255.255.0 > > +#define CONFIG_GATEWAYIP 0.0.0.0 > > +#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for= NFS */ > > + > > +#define BOOT_TARGET_DEVICES(func) \ > > + func(USB, usb, 0) \ > > + func(DHCP, dhcp, na) > > + > > +#include > > + > > +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + BOOTENV \ > > + "kernel_addr_r=3D0x202000000\0" \ > > + "fdt_addr_r=3D0x201000000\0" \ > > + "ramdisk_addr_r=3D0x206000000\0" \ > > + "fdtfile=3Dmarvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" > > + > > +/* > > + * High Level Configuration Options (easy to change) > > + */ > > +#define CONFIG_SYS_TCLK 325000000 > > + > > +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */ > > Viele Gr=C3=BC=C3=9Fe, > Stefan Roese > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de