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bh=FVntt0+Vhulj1CQmRqRPZRt4DXPoOz1uKvaLsjWZMLg=; b=TzyHnot0wW0lDEsIRjzEvPDvQa+/GEjiGhRCgk7f9yIJIevTLw/97xcTq4l3pG6FeD XUiG/beVn9Bbf0VBeaaGk67xfpTuqD6avlvwSabSGwoTqiffp2rnz2Uj19ERovzmnuDB NbqpCsjT+dsnGMgekM/FGkfXYJ1Mfk/6VJFTsyWopDxLo9A4S46KKTfgE65RAl/nTv0S lJljA5CFs2B55mBT+zOHio61R0e5M8MzodXdEQuOwOAbtaSF4VLl0YSRNtNGCMIIQQc4 vSMdm0ZGuMtKGGar61LDSqHf4btwt3uIz32oCdm8qhs5obGzT+n89RykTv00tQXvBjOA eqQQ== X-Gm-Message-State: ACrzQf1zb5NkbPbe5cXRUjVHzvI7oesPVCLP5TmRwdcvziUmn8/3vXNB uMkbSw+GMJQqXsdlworkf0V3j1zRlHH+TsvHMCc= X-Google-Smtp-Source: AMsMyM7Lq9UQ/QcOWKP2En39RSWoH1t20SnXBY0+r1ifxibGq/DD+hIlmrnoHrwme6tPhTJ7dVIB7yt7Oz+Oo1gMdsA= X-Received: by 2002:a05:6402:156:b0:440:b458:93df with SMTP id s22-20020a056402015600b00440b45893dfmr6234066edu.337.1663896480820; Thu, 22 Sep 2022 18:28:00 -0700 (PDT) MIME-Version: 1.0 References: <20220922033116.915635-1-judge.packham@gmail.com> <20220922033116.915635-6-judge.packham@gmail.com> <36b822f7-2a0f-f42f-f4aa-e44ba1aed79a@denx.de> In-Reply-To: <36b822f7-2a0f-f42f-f4aa-e44ba1aed79a@denx.de> From: Chris Packham Date: Fri, 23 Sep 2022 13:27:48 +1200 Message-ID: Subject: Re: [PATCH v4 5/5] arm: mvebu: Add RD-AC5X board To: Stefan Roese Cc: Elad Nachman , Vadym Kochan , Andre Przywara , Chris Packham , Christian Hewitt , Fabio Estevam , Marcel Ziswiler , Marek Vasut , =?UTF-8?Q?Pali_Roh=C3=A1r?= , Samuel Holland , Simon Glass , Tom Rini , "Ying-Chun Liu (PaulLiu)" , u-boot Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Thu, Sep 22, 2022 at 5:10 PM Stefan Roese wrote: > > On 22.09.22 05:31, Chris Packham wrote: > > The RD-AC5X-32G16HVG6HLG-A0 development board main components and > > features include: > > * Main 12V/54V power supply > > * 270 Gbps throughput packet processor on the main board > > * DDR4: > > * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs) > > * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs) > > * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement > > * 16GB eMMC (Samsung KLMAG1JETD-B041006) > > * 16MB SPI NOR(GD25Q127C) > > * 32 x 1000 Base-T interfaces > > * 16 x 2500 Base-T interfaces > > * SR1: 88E2540*4 > > * SR2: 88E2580*1+88E2540*2 > > * Six (6) x 25G Base-R SFP28 interfaces > > * One (1) x RJ-45 console connector, interfacing to the on board UART > > * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0) > > * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1) > > * One (1) x RJ-45 1G Base-T Management port, interfacing to the host > > port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy > > * One (1) x Oculink port, interfacing to the PCIe port for external CPU > > connection > > * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~ > > Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881 > > solution) > > * POE total power budget 780W > > * LED interfaces per network port/POE > > * LED interfaces (common) showing system status > > * PTP TC mode Supported (Reserved M.2 connector to support BC mode) > > > > Signed-off-by: Chris Packham > > --- > > > > Changes in v4: > > - Move CONFIG_DISPLAY_BOARDINFO_LATE and CONFIG_ENV_OVERWRITE to > > the defconfig. > > - Remove CONFIG_BAUDRATE as this is already set in the default config > > - Remove CONFIG_USB_MAX_CONTROLLER_COUNT as this is not needed with > > DM_USB > > - Remove CONFIG_PREBOOT as we don't have anything to run > > - Remove commented out CONFIG_BOARD_EARLY_INIT_R > > - Remove DEBUG_UART configuration > > - Remove unnecessary console environment variable > > - Remove CONFIG_MVEBU_SAR > > > > Changes in v3: > > - Remove MMC and UBIFS distroboot options (MMC driver is not currently > > functional, NAND is not populated on the RD-AC5X board) > > - Remove unnecessary Ethernet configuration > > - Remove unnecessary NAND configuration > > - Remove memory node from dts so the value passed by the DDR FW will be > > used > > > > Changes in v2: > > - Use distro boot by default > > - remove unnecessary SPI-NOR partitions > > > > arch/arm/dts/Makefile | 3 +- > > arch/arm/dts/ac5-98dx35xx-rd.dts | 129 +++++++++++++++++++++ > > arch/arm/mach-mvebu/Kconfig | 9 +- > > board/Marvell/mvebu_alleycat-5/MAINTAINERS | 6 + > > board/Marvell/mvebu_alleycat-5/Makefile | 3 + > > board/Marvell/mvebu_alleycat-5/board.c | 28 +++++ > > configs/mvebu_ac5_rd_defconfig | 84 ++++++++++++++ > > include/configs/mvebu_alleycat-5.h | 42 +++++++ > > 8 files changed, 302 insertions(+), 2 deletions(-) > > create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts > > create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS > > create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile > > create mode 100644 board/Marvell/mvebu_alleycat-5/board.c > > create mode 100644 configs/mvebu_ac5_rd_defconfig > > create mode 100644 include/configs/mvebu_alleycat-5.h > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 965895bc2a..57a5272884 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ > > cn9132-db-A.dtb \ > > cn9132-db-B.dtb \ > > cn9130-crb-A.dtb \ > > - cn9130-crb-B.dtb > > + cn9130-crb-B.dtb \ > > + ac5-98dx35xx-rd.dtb > > endif > > > > dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb > > diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts > > new file mode 100644 > > index 0000000000..d9f217cd4a > > --- /dev/null > > +++ b/arch/arm/dts/ac5-98dx35xx-rd.dts > > @@ -0,0 +1,129 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Device Tree For RD-AC5X. > > + * > > + * Copyright (C) 2021 Marvell > > + * Copyright (C) 2022 Allied Telesis Labs > > + */ > > +/* > > + * Device Tree file for Marvell Alleycat 5X development board > > + * This board file supports the B configuration of the board > > + */ > > + > > +/dts-v1/; > > + > > +#include "ac5-98dx35xx.dtsi" > > + > > +/ { > > + model = "Marvell RD-AC5X Board"; > > + compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5"; > > + > > + aliases { > > + serial0 = &uart0; > > + spiflash0 = &spiflash0; > > + gpio0 = &gpio0; > > + gpio1 = &gpio1; > > + ethernet0 = ð0; > > + ethernet1 = ð1; > > + spi0 = &spi0; > > + i2c0 = &i2c0; > > + i2c1 = &i2c1; > > + usb0 = &usb0; > > + usb1 = &usb1; > > + pinctrl0 = &pinctrl0; > > + sar-reg0 = "/config-space/sar-reg"; > > + }; > > + > > + usb1phy: usb-phy { > > + compatible = "usb-nop-xceiv"; > > + #phy-cells = <0>; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > +}; > > + > > +&uart0 { > > + status = "okay"; > > +}; > > + > > +&mdio { > > + phy0: ethernet-phy@0 { > > + reg = <0>; > > + }; > > +}; > > + > > +&i2c0 { > > + status = "okay"; > > +}; > > + > > +&i2c1 { > > + status = "okay"; > > +}; > > + > > +ð0 { > > + status = "okay"; > > + phy-handle = <&phy0>; > > +}; > > + > > +/* USB0 is a host USB */ > > +&usb0 { > > + status = "okay"; > > +}; > > + > > +/* USB1 is a peripheral USB */ > > +&usb1 { > > + status = "okay"; > > + phys = <&usb1phy>; > > + phy-names = "usb-phy"; > > + dr_mode = "peripheral"; > > +}; > > + > > +&spi0 { > > + status = "okay"; > > + > > + spiflash0: flash@0 { > > + compatible = "jedec,spi-nor"; > > + spi-max-frequency = <50000000>; > > + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ > > + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ > > + reg = <0>; > > + > > + #address-cells = <1>; > > + #size-cells = <1>; > > + }; > > +}; > > + > > +&pinctrl0 { > > + /* > > + * MPP Bus: MPP# mode# > > + * eMMC [0-11] 0x1 > > + * SPI[0] [12-17] 0x1 > > + * TSEN_INT [18] 0x1 > > + * DEV_INIT [19] 0x1 > > + * SPI[1] [20-23] 0x3 > > + * UART[1] [24-25] 0x3 > > + * I2C[0] [26-27] 0x1 > > + * XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to CPSS problem > > + * SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to CPSS problem > > + * UART[0] [32-33] 0x1 > > + * OOB_SMI [34-35] 0x1 > > + * PTP_CLK0_OUT [36] 0x1 > > + * PTP_PULSE_OUT [37] 0x1 > > + * RCVR_CLK_OUT [38] 0x1 > > + * GPIO(in/out) [39] 0x0 > > + * GPIO(in/out) [40] 0x0 > > + * PTP_REF_CLK [41] 0x1 > > + * PTP_CLK0 [42] 0x1 > > + * LED0_CLK [43] 0x1 > > + * LED0_STB [44] 0x1 > > + * LED0_DATA [45] 0x1 > > + */ > > + /* 0 1 2 3 4 5 6 7 8 9 */ > > + pin-func = < 1 1 1 1 1 1 1 1 1 1 > > + 1 1 1 1 1 1 1 1 1 1 > > + 3 3 3 3 3 3 1 1 1 1 > > + 2 2 1 1 1 1 1 1 1 0 > > + 0 1 1 1 1 1 >; > > +}; > > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig > > index 45efa24194..2120cb473f 100644 > > --- a/arch/arm/mach-mvebu/Kconfig > > +++ b/arch/arm/mach-mvebu/Kconfig > > @@ -97,7 +97,7 @@ config CUSTOMER_BOARD_SUPPORT > > bool > > > > choice > > - prompt "Armada XP/375/38x/3700/7K/8K board select" > > + prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select" > > optional > > > > config TARGET_CLEARFOG > > @@ -149,6 +149,10 @@ config TARGET_MVEBU_ARMADA_8K > > select BOARD_LATE_INIT > > imply SCSI > > > > +config TARGET_MVEBU_ALLEYCAT5 > > + bool "Support AlleyCat 5 platforms" > > + select ALLEYCAT_5 > > + > > config TARGET_OCTEONTX2_CN913x > > bool "Support CN913x platforms" > > select ARMADA_8K > > @@ -257,6 +261,7 @@ config SYS_BOARD > > default "x530" if TARGET_X530 > > default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG > > default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 > > + default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 > > > > config SYS_CONFIG_NAME > > default "clearfog" if TARGET_CLEARFOG > > @@ -277,6 +282,7 @@ config SYS_CONFIG_NAME > > default "x530" if TARGET_X530 > > default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG > > default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 > > + default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 > > > > config SYS_VENDOR > > default "Marvell" if TARGET_DB_MV784MP_GP > > @@ -296,6 +302,7 @@ config SYS_VENDOR > > default "gdsys" if TARGET_CONTROLCENTERDC > > default "alliedtelesis" if TARGET_X530 > > default "mikrotik" if TARGET_CRS3XX_98DX3236 > > + default "Marvell" if TARGET_MVEBU_ALLEYCAT5 > > > > config SYS_SOC > > default "mvebu" > > diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS > > new file mode 100644 > > index 0000000000..480c07c5f0 > > --- /dev/null > > +++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS > > @@ -0,0 +1,6 @@ > > +RD-AC5X BOARD > > +M: Chris Packham > > +S: Maintained > > +F: board/Marvell/mvebu_alleycat-5/ > > +F: include/configs/mvebu_alleycat-5.h > > +F: configs/mvebu_ac5_rd_defconfig > > diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile > > new file mode 100644 > > index 0000000000..29254b4d64 > > --- /dev/null > > +++ b/board/Marvell/mvebu_alleycat-5/Makefile > > @@ -0,0 +1,3 @@ > > +# SPDX-License-Identifier: GPL-2.0+ > > + > > +obj-y := board.o > > diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c > > new file mode 100644 > > index 0000000000..2d46775920 > > --- /dev/null > > +++ b/board/Marvell/mvebu_alleycat-5/board.c > > @@ -0,0 +1,28 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > + > > +#include > > +#include > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +int board_early_init_f(void) > > +{ > > + return 0; > > +} > > Why not remove CONFIG_BOARD_EARLY_INIT_F from defconfig and remove this > empty function? Or do you plan to add some early init code here later? > Yeah I did think about doing that. I don't have anything planned to put in these functions so I'll remove them. If it turns out I need them later I can always add them when they are needed. > > + > > +int board_early_init_r(void) > > +{ > > + return 0; > > +} > > Same for CONFIG_BOARD_EARLY_INIT_R. > > > + > > +int board_init(void) > > +{ > > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; > > + > > + return 0; > > +} > > + > > +int board_late_init(void) > > +{ > > + return 0; > > +} > > Same for CONFIG_BOARD_LATE_INIT. > > > diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig > > new file mode 100644 > > index 0000000000..610d628705 > > --- /dev/null > > +++ b/configs/mvebu_ac5_rd_defconfig > > @@ -0,0 +1,84 @@ > > +CONFIG_ARM=y > > +CONFIG_ARCH_CPU_INIT=y > > +CONFIG_ARCH_MVEBU=y > > +CONFIG_SYS_TEXT_BASE=0x200000000 > > +CONFIG_SYS_MALLOC_LEN=0x900000 > > +CONFIG_TARGET_MVEBU_ALLEYCAT5=y > > +CONFIG_ENV_SIZE=0x10000 > > +CONFIG_ENV_OFFSET=0x400000 > > +CONFIG_ENV_SECT_SIZE=0x10000 > > +CONFIG_DM_GPIO=y > > +CONFIG_SYS_LOAD_ADDR=0x202000000 > > +CONFIG_SYS_MEMTEST_START=0x200800000 > > +CONFIG_SYS_MEMTEST_END=0x200ffffff > > +CONFIG_DISTRO_DEFAULTS=y > > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000 > > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > > +CONFIG_FIT=y > > +CONFIG_BOOTDELAY=-1 > > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y > > +CONFIG_SYS_CONSOLE_INFO_QUIET=y > > +CONFIG_DISPLAY_BOARDINFO_LATE=y > > +CONFIG_ARCH_EARLY_INIT_R=y > > +CONFIG_ARCH_MISC_INIT=y > > +CONFIG_BOARD_EARLY_INIT_F=y > > +CONFIG_CMD_BOOTZ=y > > +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 > > +CONFIG_CMD_MEMTEST=y > > +# CONFIG_CMD_FLASH is not set > > +CONFIG_CMD_GPIO=y > > +CONFIG_CMD_I2C=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_PCI=y > > +CONFIG_CMD_SPI=y > > +CONFIG_CMD_USB=y > > +# CONFIG_CMD_SETEXPR is not set > > +CONFIG_CMD_CACHE=y > > +CONFIG_CMD_TIME=y > > +CONFIG_CMD_MVEBU_BUBT=y > > +CONFIG_CMD_REGULATOR=y > > +CONFIG_CMD_EXT4_WRITE=y > > +CONFIG_CMD_UBI=y > > +CONFIG_MAC_PARTITION=y > > +CONFIG_OF_EMBED=y > > IIRC, this option is deprecated. Compiling should complain about > this. Do you really need this? > Doesn't appear to. OF_SEPARATE should work for me. > > +CONFIG_ENV_OVERWRITE=y > > +CONFIG_ENV_IS_IN_SPI_FLASH=y > > +CONFIG_CLK=y > > +CONFIG_CLK_MVEBU=y > > +CONFIG_DM_PCA953X=y > > +CONFIG_DM_I2C=y > > +CONFIG_SYS_I2C_MVTWSI=y > > +CONFIG_MISC=y > > +CONFIG_MMC_SDHCI=y > > +CONFIG_MMC_SDHCI_XENON=y > > +CONFIG_MTD=y > > +CONFIG_SPI_FLASH_GIGADEVICE=y > > +CONFIG_SPI_FLASH_MACRONIX=y > > +CONFIG_SPI_FLASH_SPANSION=y > > +CONFIG_SPI_FLASH_STMICRO=y > > +CONFIG_PHY_MARVELL=y > > +CONFIG_PHY_GIGE=y > > +CONFIG_E1000=y > > Really? Do you have PCI enabled? > The board does have a PCI connector on it but by now I think I've dropped pretty much any of the vendor code that would allow it to be used. I'll drop this and the PCI=y below. > > +CONFIG_MVNETA=y > > +CONFIG_MVMDIO=y > > +CONFIG_PCI=y > > +CONFIG_PHY=y > > +CONFIG_PINCTRL=y > > +CONFIG_PINCTRL_ARMADA_8K=y > > +CONFIG_DM_REGULATOR_FIXED=y > > +CONFIG_DM_REGULATOR_GPIO=y > > +CONFIG_DM_RTC=y > > +CONFIG_DM_SCSI=y > > +CONFIG_SYS_NS16550=y > > +CONFIG_MVEBU_A3700_SPI=y > > +CONFIG_DM_THERMAL=y > > +CONFIG_USB=y > > +CONFIG_USB_XHCI_HCD=y > > +CONFIG_USB_EHCI_HCD=y > > +CONFIG_USB_HOST_ETHER=y > > +CONFIG_USB_ETHER_ASIX=y > > +CONFIG_USB_ETHER_ASIX88179=y > > +CONFIG_USB_ETHER_MCS7830=y > > +CONFIG_USB_ETHER_RTL8152=y > > +CONFIG_USB_ETHER_SMSC95XX=y > > diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h > > new file mode 100644 > > index 0000000000..41bdfae6c3 > > --- /dev/null > > +++ b/include/configs/mvebu_alleycat-5.h > > @@ -0,0 +1,42 @@ > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > +/* > > + * Copyright (C) 2018 Marvell International Ltd > > + */ > > + > > +#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H > > +#define _CONFIG_MVEBU_ALLEYCAY_5_H > > + > > +#include > > + > > +/* additions for new ARM relocation support */ > > +#define CONFIG_SYS_SDRAM_BASE 0x200000000 > > + > > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ > > + 115200, 230400, 460800, 921600 } > > + > > +/* Default Env vars */ > > +#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */ > > +#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */ > > +#define CONFIG_NETMASK 255.255.255.0 > > +#define CONFIG_GATEWAYIP 0.0.0.0 > > +#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for NFS */ > > + > > +#define BOOT_TARGET_DEVICES(func) \ > > + func(USB, usb, 0) \ > > + func(DHCP, dhcp, na) > > + > > +#include > > + > > +#define CONFIG_EXTRA_ENV_SETTINGS \ > > + BOOTENV \ > > + "kernel_addr_r=0x202000000\0" \ > > + "fdt_addr_r=0x201000000\0" \ > > + "ramdisk_addr_r=0x206000000\0" \ > > + "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" > > + > > +/* > > + * High Level Configuration Options (easy to change) > > + */ > > +#define CONFIG_SYS_TCLK 325000000 > > + > > +#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */ > BTW: Did you run checkpatch.pl on the series? This might give some > further ideas on cleanup. Yes I have been (via patman). It's pretty clean now (a couple of warning/check messages that I'm electing to leave). > > Thanks, > Stefan