From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AD26C282CC for ; Tue, 5 Feb 2019 06:05:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5BB1D2175B for ; Tue, 5 Feb 2019 06:05:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mobiveil.co.in header.i=@mobiveil.co.in header.b="q0302VE6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727398AbfBEGFw (ORCPT ); Tue, 5 Feb 2019 01:05:52 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40253 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726985AbfBEGFw (ORCPT ); Tue, 5 Feb 2019 01:05:52 -0500 Received: by mail-wm1-f66.google.com with SMTP id f188so2268743wmf.5 for ; Mon, 04 Feb 2019 22:05:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mobiveil.co.in; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jcZjY5XDE/E9FNQRkXQrr6M7zvi/tvQDKDvX/q8jeBg=; b=q0302VE6ZZ4eNwzx+A/WjcR8zgl6JfM1E9Cb7sWFs3EnBG8DlBam36U/zaUIomk+Rn PB/UJi6qNDOJeNoxyP5YBBm6F/SKwfXjCV6humG+s32dhAo5O4Sl7rjWXrfNAFmkdcZS ah15QIs+ac7BXFU+SI+Ree7g0rLUefx4a1/00= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jcZjY5XDE/E9FNQRkXQrr6M7zvi/tvQDKDvX/q8jeBg=; b=DHpGfTnvL6GAXOkLWQpzPDYbEneQzeA219BrKbEQmY14kprmh1u51mbmZtg3u7UzwU MQJeXFCC8tmKRJ4xYGOKvWDv9QMxfLA9juGfQilslXyE3GI+CGySRtjRPnGIbXwu2qnv Aem79j69dFagV8yR2G48pJDhYKre2N5Y9cTfBR0vXbIAIFisbeD09D344kLlN4QZ0NKz 3BDDsTS+cCRswp0Sl8Sigcp8x/fTK4KkG6l0kEDTwQCTNt25HlzMTkLZG7dfSggOhCMj tLB+FCNw/uQ3Oj+4dF7MWKF64Wl5LZK1Q7LWwOOHnLCJN82WsLD8q0mFrWIlWRZXr+kZ Q+mg== X-Gm-Message-State: AHQUAub9QCpJQSZHWG+4oQnSV2qiakms+ZThqjTglwZ/b3QVYaAVvU2H hX5YAfGoQXtq33IKaT5DvwinwIIXrOlKTWEuDBe2Fg== X-Google-Smtp-Source: AHgI3IZJKwW71eEFV/3N1NOzT6DuLNVD97wOcuHi4aYiIwiKY7zBlO5L43hFAXGP2PhSDNVMebdU2WxBXYVABu5rJ6Y= X-Received: by 2002:a1c:9e4a:: with SMTP id h71mr2241827wme.82.1549346750647; Mon, 04 Feb 2019 22:05:50 -0800 (PST) MIME-Version: 1.0 References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-9-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190129080926.36773-9-Zhiqiang.Hou@nxp.com> From: Subrahmanya Lingappa Date: Tue, 5 Feb 2019 11:38:24 +0530 Message-ID: Subject: Re: [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reviewed-by: Subrahmanya Lingappa On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > The inbound windows have different register set with outbound windows. > This patch change the MEM inbound window to the first one. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index df71c11b4810..e88afc792a5c 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); > > /* memory inbound translation window */ > - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); > + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); > > /* Get the I/O and memory ranges from DT */ > resource_list_for_each_entry(win, &pcie->resources) { > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subrahmanya Lingappa Subject: Re: [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Date: Tue, 5 Feb 2019 11:38:24 +0530 Message-ID: References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-9-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20190129080926.36773-9-Zhiqiang.Hou@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao List-Id: devicetree@vger.kernel.org Reviewed-by: Subrahmanya Lingappa On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > The inbound windows have different register set with outbound windows. > This patch change the MEM inbound window to the first one. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index df71c11b4810..e88afc792a5c 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); > > /* memory inbound translation window */ > - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); > + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); > > /* Get the I/O and memory ranges from DT */ > resource_list_for_each_entry(win, &pcie->resources) { > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B639C282CB for ; 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Mon, 04 Feb 2019 22:05:50 -0800 (PST) MIME-Version: 1.0 References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-9-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190129080926.36773-9-Zhiqiang.Hou@nxp.com> From: Subrahmanya Lingappa Date: Tue, 5 Feb 2019 11:38:24 +0530 Message-ID: Subject: Re: [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions To: "Z.q. Hou" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190204_220552_619473_003A74DD X-CRM114-Status: GOOD ( 14.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , Xiaowei Bao , "linux-pci@vger.kernel.org" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Leo Li , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , "catalin.marinas@arm.com" , "bhelgaas@google.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Reviewed-by: Subrahmanya Lingappa On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > The inbound windows have different register set with outbound windows. > This patch change the MEM inbound window to the first one. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index df71c11b4810..e88afc792a5c 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -616,7 +616,7 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res)); > > /* memory inbound translation window */ > - program_ib_windows(pcie, WIN_NUM_1, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); > + program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); > > /* Get the I/O and memory ranges from DT */ > resource_list_for_each_entry(win, &pcie->resources) { > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel