From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47C58C282D7 for ; Tue, 5 Feb 2019 06:04:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 162712146F for ; Tue, 5 Feb 2019 06:04:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mobiveil.co.in header.i=@mobiveil.co.in header.b="a0lt9vja" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727133AbfBEGEY (ORCPT ); Tue, 5 Feb 2019 01:04:24 -0500 Received: from mail-wr1-f66.google.com ([209.85.221.66]:44728 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725934AbfBEGEX (ORCPT ); Tue, 5 Feb 2019 01:04:23 -0500 Received: by mail-wr1-f66.google.com with SMTP id v16so410451wrn.11 for ; Mon, 04 Feb 2019 22:04:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mobiveil.co.in; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=E8Nz/JOD+e1xoqAI4YK+0goMEU7txF8Kn0+PiGymNa8=; b=a0lt9vjaYGvo5ZjCMKI4qBCmuxJB3MEqbdXjeKZbh+T2f2nZ72O8/RHqWxV7l6HJYZ UCE2tm6/FROvTqIC+Nj4Xtk13boNIRpa4eHoE2/95EH9a+MyYFmfR2YIAwrsfxbWN3ol k0v2t9jjDyZw3M4IrxpaQEeGGibrzRh/SKAfI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=E8Nz/JOD+e1xoqAI4YK+0goMEU7txF8Kn0+PiGymNa8=; b=Pn1cUPnI5jpqEA1hVgc/CJIgfVfc+BuBxgU1t9+AfgSDnfnQgMjbRIzrDcvtl9k5k5 lkHJzJ2Q4duwLKwPLxh/IajuQzQzgqVtyH8LSuRbfau9XosV9kEIRZmhVPGqKW6gAc8I TTZRuzgcvoe3piOajl1NOPa3QSMxKE4XzoRmkVYrJm06MP9saOcM3F3pfpGLCeB+lBt8 d8bxL3aKSNM+DUQLCnv7aL0KgTfk0DMWkUze4jTjBNHvTgTBp5hYRGsjFynpxK2XfnZ/ IS0MIlBCmEhFYp7LxN89TyZc8RVItLxT3hx1owm5LMSfYYRYYwMgzgtrfqodh8Dh0s+o hRgg== X-Gm-Message-State: AHQUAuYQ1KVWlnUBWkE+cwFkcd1hKdMyAOq3mqLy5LJBM77UpOKo6ERU u2ygQJGI4KEJBuFdlBy4kZSYUg2cHiF7EBmTcJxDxg== X-Google-Smtp-Source: AHgI3IZABnEpCunPrjrSCncSfkYCrTT1Vrxws6KuAXMByp9HYmZCCEG2EFEppAWPTIq00CvmKwpJrXSlEI29F2o99Mw= X-Received: by 2002:adf:fd81:: with SMTP id d1mr2123021wrr.105.1549346662212; Mon, 04 Feb 2019 22:04:22 -0800 (PST) MIME-Version: 1.0 References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-6-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190129080926.36773-6-Zhiqiang.Hou@nxp.com> From: Subrahmanya Lingappa Date: Tue, 5 Feb 2019 11:36:56 +0530 Message-ID: Subject: Re: [PATCHv3 05/27] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reviewed-by: Subrahmanya Lingappa On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > It should get PCI base address from the DT node property 'ranges' > to setup MEM/IO outbound windows instead of always zero. > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge > IP driver") > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index a0dd337c6214..8ff873023b5f 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -630,8 +630,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > > /* configure outbound translation window */ > program_ob_windows(pcie, pcie->ob_wins_configured, > - win->res->start, 0, type, > - resource_size(win->res)); > + win->res->start, > + win->res->start - win->offset, > + type, resource_size(win->res)); > } > > /* setup MSI hardware registers */ > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subrahmanya Lingappa Subject: Re: [PATCHv3 05/27] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Date: Tue, 5 Feb 2019 11:36:56 +0530 Message-ID: References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-6-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20190129080926.36773-6-Zhiqiang.Hou@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao List-Id: devicetree@vger.kernel.org Reviewed-by: Subrahmanya Lingappa On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > It should get PCI base address from the DT node property 'ranges' > to setup MEM/IO outbound windows instead of always zero. > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge > IP driver") > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index a0dd337c6214..8ff873023b5f 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -630,8 +630,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > > /* configure outbound translation window */ > program_ob_windows(pcie, pcie->ob_wins_configured, > - win->res->start, 0, type, > - resource_size(win->res)); > + win->res->start, > + win->res->start - win->offset, > + type, resource_size(win->res)); > } > > /* setup MSI hardware registers */ > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F916C282CB for ; Tue, 5 Feb 2019 06:04:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D47582145D for ; Tue, 5 Feb 2019 06:04:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="K+vhaG0O"; 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Hou" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190204_220423_986015_BF057392 X-CRM114-Status: GOOD ( 13.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , Xiaowei Bao , "linux-pci@vger.kernel.org" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Leo Li , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , "catalin.marinas@arm.com" , "bhelgaas@google.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Reviewed-by: Subrahmanya Lingappa On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > It should get PCI base address from the DT node property 'ranges' > to setup MEM/IO outbound windows instead of always zero. > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge > IP driver") > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > drivers/pci/controller/pcie-mobiveil.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index a0dd337c6214..8ff873023b5f 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -630,8 +630,9 @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie) > > /* configure outbound translation window */ > program_ob_windows(pcie, pcie->ob_wins_configured, > - win->res->start, 0, type, > - resource_size(win->res)); > + win->res->start, > + win->res->start - win->offset, > + type, resource_size(win->res)); > } > > /* setup MSI hardware registers */ > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel