From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEC73C169C4 for ; Fri, 8 Feb 2019 12:42:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9EFF82086C for ; Fri, 8 Feb 2019 12:42:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mobiveil.co.in header.i=@mobiveil.co.in header.b="LTW9Gy9V" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727069AbfBHMmT (ORCPT ); Fri, 8 Feb 2019 07:42:19 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:41896 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726522AbfBHMmT (ORCPT ); Fri, 8 Feb 2019 07:42:19 -0500 Received: by mail-wr1-f68.google.com with SMTP id x10so3401295wrs.8 for ; Fri, 08 Feb 2019 04:42:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mobiveil.co.in; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FcNSWtz/94EAq7Zt0ztZtaogVS62SwmBQ8CLMNUPaIE=; b=LTW9Gy9VdLkzCaQ8/6LR1RN5CMBX4DNv4zx8Vt+n9WPe5s5U2j2SkWi9d6uJPlV/zx q2zfeEvtPuL0+gE773N8fRvWzd+7hhAGOqytTlwdAVErVEIm+4ioBVY8sc175wb7NQiV F8Ywgr5UzWMCXiEm92JA1qgPgSj1rA8WtsmdE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FcNSWtz/94EAq7Zt0ztZtaogVS62SwmBQ8CLMNUPaIE=; b=UBHVaioXlHrRwgOKH6FZ0fOdI1f4uTLOrKS69710JnTB+UQ+EpCGsQjhD0FivOHrZk 2bcVmqxRwqTp7eAhUtJoXJQOxhp51bpfF+CpIBcLw5/qin9iW+FGSJlg3bz/renFsgTn QNHPQbJHZFiayobOIQgX02rGpvphsTWChAitDWktEocYnrpYG87xRXNmHyNChPXMmGbT NbgH07S7ttx5WGQGE2DNMWBypXaqvV4NFqlxVZ5+LmVt3Ss98CAP8Ace5cdz6XdguphT j2kN/VzewvKFgApTG9G3oebdPn8i9PNqVe016v9ERQuL8R/zxojqCPrdNJ6sg/zxa8DG 05AA== X-Gm-Message-State: AHQUAuYVn/u5lBLrh2o8PXxwFFPFaC71xcfgRh3amBckvDYUtmpvtCxf lNX6PvxHVTtzDhf+U0ITlNJbe0Sd5rB1b1uKMRlIww== X-Google-Smtp-Source: AHgI3IaFmjXxGwVIVl/tppCIeLz9HYPH8Ihh1C5K04cAMhMPJi87YuzbKG67WoAepyYFp1mHlKOJKR7kpdPF70VdDj4= X-Received: by 2002:adf:fd81:: with SMTP id d1mr16532537wrr.105.1549629737745; Fri, 08 Feb 2019 04:42:17 -0800 (PST) MIME-Version: 1.0 References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-21-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190129080926.36773-21-Zhiqiang.Hou@nxp.com> From: Subrahmanya Lingappa Date: Fri, 8 Feb 2019 18:14:57 +0530 Message-ID: Subject: Re: [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > As there are some Byte and Half-Work width registers in PCIe > configuration space, add Byte and Half-Word width register > accessors. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > index 81685840b378..933c2f34bc52 100644 > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > @@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) > return csr_read(pcie, off, 0x4); > } > > +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x2); > +} > + > +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x1); > +} > + > static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) > { > csr_write(pcie, val, off, 0x4); > } > > +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x2); > +} > + > +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x1); > +} > + > #endif /* _PCIE_MOBIVEIL_H */ > -- > 2.17.1 > Reviewed-by: Subrahmanya Lingappa From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subrahmanya Lingappa Subject: Re: [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors Date: Fri, 8 Feb 2019 18:14:57 +0530 Message-ID: References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-21-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20190129080926.36773-21-Zhiqiang.Hou@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao List-Id: devicetree@vger.kernel.org On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > As there are some Byte and Half-Work width registers in PCIe > configuration space, add Byte and Half-Word width register > accessors. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > index 81685840b378..933c2f34bc52 100644 > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > @@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) > return csr_read(pcie, off, 0x4); > } > > +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x2); > +} > + > +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x1); > +} > + > static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) > { > csr_write(pcie, val, off, 0x4); > } > > +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x2); > +} > + > +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x1); > +} > + > #endif /* _PCIE_MOBIVEIL_H */ > -- > 2.17.1 > Reviewed-by: Subrahmanya Lingappa From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01B97C282CB for ; Fri, 8 Feb 2019 12:42:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C6FB8217D8 for ; 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Fri, 08 Feb 2019 04:42:17 -0800 (PST) MIME-Version: 1.0 References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129080926.36773-21-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190129080926.36773-21-Zhiqiang.Hou@nxp.com> From: Subrahmanya Lingappa Date: Fri, 8 Feb 2019 18:14:57 +0530 Message-ID: Subject: Re: [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors To: "Z.q. Hou" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_044221_550512_10538C35 X-CRM114-Status: GOOD ( 13.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , Xiaowei Bao , "linux-pci@vger.kernel.org" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Leo Li , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , "catalin.marinas@arm.com" , "bhelgaas@google.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote: > > From: Hou Zhiqiang > > As there are some Byte and Half-Work width registers in PCIe > configuration space, add Byte and Half-Word width register > accessors. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > --- > V3: > - No change > > .../pci/controller/mobiveil/pcie-mobiveil.h | 20 +++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > index 81685840b378..933c2f34bc52 100644 > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h > @@ -181,9 +181,29 @@ static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) > return csr_read(pcie, off, 0x4); > } > > +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x2); > +} > + > +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x1); > +} > + > static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) > { > csr_write(pcie, val, off, 0x4); > } > > +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x2); > +} > + > +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x1); > +} > + > #endif /* _PCIE_MOBIVEIL_H */ > -- > 2.17.1 > Reviewed-by: Subrahmanya Lingappa _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel