From: Ley Foon Tan <lftan.linux@gmail.com>
To: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: ZY - u-boot <u-boot@lists.denx.de>, Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Tien Fong Chee <tien.fong.chee@intel.com>,
Dalon Westergreen <dalon.westergreen@intel.com>,
Simon Glass <sjg@chromium.org>,
Yau Wai Gan <yau.wai.gan@intel.com>
Subject: Re: [v3 05/17] drivers: clk: Add clock driver for Intel N5X device
Date: Fri, 9 Jul 2021 00:17:29 +0800 [thread overview]
Message-ID: <CAFiDJ58PcCv7Hua639foNW9vFX0Fjgn==mb=gZ=pPKZjA2ynEA@mail.gmail.com> (raw)
In-Reply-To: <20210613084852.30868-6-elly.siew.chin.lim@intel.com>
On Sun, Jun 13, 2021 at 4:49 PM Siew Chin Lim
<elly.siew.chin.lim@intel.com> wrote:
>
> Add clock manager driver for N5X. Provides clock initialization
> and get_rate functions.
>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
>
> ---
> v3:
> - Use BIT() macro for CLKMGR_INTER_*_MASK macro
>
> v2:
> - common.h need to be included before clock_manager.h
> - Remove unnecessary comment : write 1 to clear
> - Remove unnecessary () in the code
> ---
> drivers/clk/altera/Makefile | 3 +-
> drivers/clk/altera/clk-n5x.c | 489 ++++++++++++++++++++++++++
> drivers/clk/altera/clk-n5x.h | 217 ++++++++++++
> include/dt-bindings/clock/n5x-clock.h | 71 ++++
> 4 files changed, 779 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/altera/clk-n5x.c
> create mode 100644 drivers/clk/altera/clk-n5x.h
> create mode 100644 include/dt-bindings/clock/n5x-clock.h
Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
Regards
Ley Foon
next prev parent reply other threads:[~2021-07-08 16:17 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-13 8:48 [v3 00/17] Add Intel N5X SoC support Siew Chin Lim
2021-06-13 8:48 ` [v3 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function Siew Chin Lim
2021-06-13 8:48 ` [v3 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h Siew Chin Lim
2021-06-13 8:48 ` [v3 03/17] arm: socfpga: Add base address for Intel N5X device Siew Chin Lim
2021-06-13 8:48 ` [v3 04/17] arm: socfpga: Add handoff data support " Siew Chin Lim
2021-07-08 16:15 ` Ley Foon Tan
2021-06-13 8:48 ` [v3 05/17] drivers: clk: Add clock driver " Siew Chin Lim
2021-07-08 16:17 ` Ley Foon Tan [this message]
2021-06-13 8:48 ` [v3 06/17] arm: socfpga: Get clock manager base address " Siew Chin Lim
2021-06-13 8:48 ` [v3 07/17] drivers: clk: Add memory clock driver " Siew Chin Lim
2021-07-08 16:19 ` Ley Foon Tan
2021-06-13 8:48 ` [v3 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h Siew Chin Lim
2021-06-13 8:48 ` [v3 09/17] arm: socfpga: Add clock manager for Intel N5X device Siew Chin Lim
2021-06-13 8:48 ` [v3 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c Siew Chin Lim
2021-06-13 8:48 ` [v3 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB Siew Chin Lim
2021-06-13 8:48 ` [v3 12/17] ddr: altera: Add SDRAM driver for Intel N5X device Siew Chin Lim
2021-07-08 17:06 ` Ley Foon Tan
2021-06-13 8:48 ` [v3 13/17] arm: socfpga: Add SPL " Siew Chin Lim
2021-06-13 8:48 ` [v3 14/17] board: intel: Add socdk board support " Siew Chin Lim
2021-06-13 8:48 ` [v3 15/17] arm: dts: Add base dtsi and devkit dts " Siew Chin Lim
2021-07-08 16:32 ` Ley Foon Tan
2021-07-09 1:10 ` Lim, Elly Siew Chin
2021-06-13 8:48 ` [v3 16/17] include: configs: Add Intel N5X device CONFIGs Siew Chin Lim
2021-06-13 8:48 ` [v3 17/17] arm: socfpga: Enable Intel N5X device build Siew Chin Lim
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