From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vivek Gautam Subject: Re: [PATCH v12 1/4] iommu/arm-smmu: Add pm_runtime/sleep ops Date: Thu, 12 Jul 2018 16:27:25 +0530 Message-ID: References: <20180708173413.1965-1-vivek.gautam@codeaurora.org> <20180708173413.1965-2-vivek.gautam@codeaurora.org> <17407514.unFVTGoGrn@aspire.rjw.lan> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: Tomasz Figa Cc: Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux PM , sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, "Rafael J. Wysocki" , "Rafael J. Wysocki" , Will Deacon , Linux Kernel Mailing List , "list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS , Joerg Roedel , " , Rob Herring , linux-arm-msm , freedreno List-Id: linux-arm-msm@vger.kernel.org SGksCgoKT24gV2VkLCBKdWwgMTEsIDIwMTggYXQgNjoyMSBQTSwgVG9tYXN6IEZpZ2EgPHRmaWdh QGNocm9taXVtLm9yZz4gd3JvdGU6Cj4gT24gV2VkLCBKdWwgMTEsIDIwMTggYXQgODoxMSBQTSBS YWZhZWwgSi4gV3lzb2NraSA8cmFmYWVsQGtlcm5lbC5vcmc+IHdyb3RlOgo+Pgo+PiBPbiBXZWQs IEp1bCAxMSwgMjAxOCBhdCAxMjo1NSBQTSwgVml2ZWsgR2F1dGFtCj4+IDx2aXZlay5nYXV0YW1A Y29kZWF1cm9yYS5vcmc+IHdyb3RlOgo+PiA+IEhpIFJhZmFlbCwKPj4gPgo+PiA+Cj4+ID4gT24g V2VkLCBKdWwgMTEsIDIwMTggYXQgMzoyMCBQTSwgUmFmYWVsIEouIFd5c29ja2kgPHJqd0Byand5 c29ja2kubmV0PiB3cm90ZToKPj4gPj4gT24gU3VuZGF5LCBKdWx5IDgsIDIwMTggNzozNDoxMCBQ TSBDRVNUIFZpdmVrIEdhdXRhbSB3cm90ZToKPj4gPj4+IEZyb206IFNyaWNoYXJhbiBSIDxzcmlj aGFyYW5AY29kZWF1cm9yYS5vcmc+Cj4+ID4+Pgo+PiA+Pj4gVGhlIHNtbXUgbmVlZHMgdG8gYmUg ZnVuY3Rpb25hbCBvbmx5IHdoZW4gdGhlIHJlc3BlY3RpdmUKPj4gPj4+IG1hc3RlcidzIHVzaW5n IGl0IGFyZSBhY3RpdmUuIFRoZSBkZXZpY2VfbGluayBmZWF0dXJlCj4+ID4+PiBoZWxwcyB0byB0 cmFjayBzdWNoIGZ1bmN0aW9uYWwgZGVwZW5kZW5jaWVzLCBzbyB0aGF0IHRoZQo+PiA+Pj4gaW9t bXUgZ2V0cyBwb3dlcmVkIHdoZW4gdGhlIG1hc3RlciBkZXZpY2UgZW5hYmxlcyBpdHNlbGYKPj4g Pj4+IHVzaW5nIHBtX3J1bnRpbWUuIFNvIGJ5IGFkYXB0aW5nIHRoZSBzbW11IGRyaXZlciBmb3IK Pj4gPj4+IHJ1bnRpbWUgcG0sIGFib3ZlIHNhaWQgZGVwZW5kZW5jeSBjYW4gYmUgYWRkcmVzc2Vk Lgo+PiA+Pj4KPj4gPj4+IFRoaXMgcGF0Y2ggYWRkcyB0aGUgcG0gcnVudGltZS9zbGVlcCBjYWxs YmFja3MgdG8gdGhlCj4+ID4+PiBkcml2ZXIgYW5kIGFsc28gdGhlIGZ1bmN0aW9ucyB0byBwYXJz ZSB0aGUgc21tdSBjbG9ja3MKPj4gPj4+IGZyb20gRFQgYW5kIGVuYWJsZSB0aGVtIGluIHJlc3Vt ZS9zdXNwZW5kLgo+PiA+Pj4KPj4gPj4+IFNpZ25lZC1vZmYtYnk6IFNyaWNoYXJhbiBSIDxzcmlj aGFyYW5AY29kZWF1cm9yYS5vcmc+Cj4+ID4+PiBTaWduZWQtb2ZmLWJ5OiBBcmNoaXQgVGFuZWph IDxhcmNoaXR0QGNvZGVhdXJvcmEub3JnPgo+PiA+Pj4gW3ZpdmVrOiBDbG9jayByZXdvcmsgdG8g cmVxdWVzdCBidWxrIG9mIGNsb2Nrc10KPj4gPj4+IFNpZ25lZC1vZmYtYnk6IFZpdmVrIEdhdXRh bSA8dml2ZWsuZ2F1dGFtQGNvZGVhdXJvcmEub3JnPgo+PiA+Pj4gUmV2aWV3ZWQtYnk6IFRvbWFz eiBGaWdhIDx0ZmlnYUBjaHJvbWl1bS5vcmc+Cj4+ID4+PiAtLS0KPj4gPj4+Cj4+ID4+PiAgLSBO byBjaGFuZ2Ugc2luY2UgdjExLgo+PiA+Pj4KPj4gPj4+ICBkcml2ZXJzL2lvbW11L2FybS1zbW11 LmMgfCA2MCArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrLS0K Pj4gPj4+ICAxIGZpbGUgY2hhbmdlZCwgNTggaW5zZXJ0aW9ucygrKSwgMiBkZWxldGlvbnMoLSkK Pj4gPj4+Cj4+ID4+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9pb21tdS9hcm0tc21tdS5jIGIvZHJp dmVycy9pb21tdS9hcm0tc21tdS5jCj4+ID4+PiBpbmRleCBmN2E5NmJjZjk0YTYuLmEwMWQwZGRl MjFkZCAxMDA2NDQKPj4gPj4+IC0tLSBhL2RyaXZlcnMvaW9tbXUvYXJtLXNtbXUuYwo+PiA+Pj4g KysrIGIvZHJpdmVycy9pb21tdS9hcm0tc21tdS5jCj4+ID4+PiBAQCAtNDgsNiArNDgsNyBAQAo+ PiA+Pj4gICNpbmNsdWRlIDxsaW51eC9vZl9pb21tdS5oPgo+PiA+Pj4gICNpbmNsdWRlIDxsaW51 eC9wY2kuaD4KPj4gPj4+ICAjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+Cj4+ID4+ PiArI2luY2x1ZGUgPGxpbnV4L3BtX3J1bnRpbWUuaD4KPj4gPj4+ICAjaW5jbHVkZSA8bGludXgv c2xhYi5oPgo+PiA+Pj4gICNpbmNsdWRlIDxsaW51eC9zcGlubG9jay5oPgo+PiA+Pj4KPj4gPj4+ IEBAIC0yMDUsNiArMjA2LDggQEAgc3RydWN0IGFybV9zbW11X2RldmljZSB7Cj4+ID4+PiAgICAg ICB1MzIgICAgICAgICAgICAgICAgICAgICAgICAgICAgIG51bV9nbG9iYWxfaXJxczsKPj4gPj4+ ICAgICAgIHUzMiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgbnVtX2NvbnRleHRfaXJxczsK Pj4gPj4+ICAgICAgIHVuc2lnbmVkIGludCAgICAgICAgICAgICAgICAgICAgKmlycXM7Cj4+ID4+ PiArICAgICBzdHJ1Y3QgY2xrX2J1bGtfZGF0YSAgICAgICAgICAgICpjbGtzOwo+PiA+Pj4gKyAg ICAgaW50ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBudW1fY2xrczsKPj4gPj4+Cj4+ID4+ PiAgICAgICB1MzIgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGNhdml1bV9pZF9iYXNlOyAv KiBTcGVjaWZpYyB0byBDYXZpdW0gKi8KPj4gPj4+Cj4+ID4+PiBAQCAtMTg5NywxMCArMTkwMCwx MiBAQCBzdGF0aWMgaW50IGFybV9zbW11X2RldmljZV9jZmdfcHJvYmUoc3RydWN0IGFybV9zbW11 X2RldmljZSAqc21tdSkKPj4gPj4+ICBzdHJ1Y3QgYXJtX3NtbXVfbWF0Y2hfZGF0YSB7Cj4+ID4+ PiAgICAgICBlbnVtIGFybV9zbW11X2FyY2hfdmVyc2lvbiB2ZXJzaW9uOwo+PiA+Pj4gICAgICAg ZW51bSBhcm1fc21tdV9pbXBsZW1lbnRhdGlvbiBtb2RlbDsKPj4gPj4+ICsgICAgIGNvbnN0IGNo YXIgKiBjb25zdCAqY2xrczsKPj4gPj4+ICsgICAgIGludCBudW1fY2xrczsKPj4gPj4+ICB9Owo+ PiA+Pj4KPj4gPj4+ICAjZGVmaW5lIEFSTV9TTU1VX01BVENIX0RBVEEobmFtZSwgdmVyLCBpbXAp ICBcCj4+ID4+PiAtc3RhdGljIHN0cnVjdCBhcm1fc21tdV9tYXRjaF9kYXRhIG5hbWUgPSB7IC52 ZXJzaW9uID0gdmVyLCAubW9kZWwgPSBpbXAgfQo+PiA+Pj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg YXJtX3NtbXVfbWF0Y2hfZGF0YSBuYW1lID0geyAudmVyc2lvbiA9IHZlciwgLm1vZGVsID0gaW1w IH0KPj4gPj4+Cj4+ID4+PiAgQVJNX1NNTVVfTUFUQ0hfREFUQShzbW11X2dlbmVyaWNfdjEsIEFS TV9TTU1VX1YxLCBHRU5FUklDX1NNTVUpOwo+PiA+Pj4gIEFSTV9TTU1VX01BVENIX0RBVEEoc21t dV9nZW5lcmljX3YyLCBBUk1fU01NVV9WMiwgR0VORVJJQ19TTU1VKTsKPj4gPj4+IEBAIC0xOTE5 LDYgKzE5MjQsMjMgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9kZXZpY2VfaWQgYXJtX3NtbXVf b2ZfbWF0Y2hbXSA9IHsKPj4gPj4+ICB9Owo+PiA+Pj4gIE1PRFVMRV9ERVZJQ0VfVEFCTEUob2Ys IGFybV9zbW11X29mX21hdGNoKTsKPj4gPj4+Cj4+ID4+PiArc3RhdGljIHZvaWQgYXJtX3NtbXVf ZmlsbF9jbGtfZGF0YShzdHJ1Y3QgYXJtX3NtbXVfZGV2aWNlICpzbW11LAo+PiA+Pj4gKyAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgY29uc3QgY2hhciAqIGNvbnN0ICpjbGtzKQo+PiA+ Pj4gK3sKPj4gPj4+ICsgICAgIGludCBpOwo+PiA+Pj4gKwo+PiA+Pj4gKyAgICAgaWYgKHNtbXUt Pm51bV9jbGtzIDwgMSkKPj4gPj4+ICsgICAgICAgICAgICAgcmV0dXJuOwo+PiA+Pj4gKwo+PiA+ Pj4gKyAgICAgc21tdS0+Y2xrcyA9IGRldm1fa2NhbGxvYyhzbW11LT5kZXYsIHNtbXUtPm51bV9j bGtzLAo+PiA+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBzaXplb2YoKnNtbXUt PmNsa3MpLCBHRlBfS0VSTkVMKTsKPj4gPj4+ICsgICAgIGlmICghc21tdS0+Y2xrcykKPj4gPj4+ ICsgICAgICAgICAgICAgcmV0dXJuOwo+PiA+Pj4gKwo+PiA+Pj4gKyAgICAgZm9yIChpID0gMDsg aSA8IHNtbXUtPm51bV9jbGtzOyBpKyspCj4+ID4+PiArICAgICAgICAgICAgIHNtbXUtPmNsa3Nb aV0uaWQgPSBjbGtzW2ldOwo+PiA+Pj4gK30KPj4gPj4+ICsKPj4gPj4+ICAjaWZkZWYgQ09ORklH X0FDUEkKPj4gPj4+ICBzdGF0aWMgaW50IGFjcGlfc21tdV9nZXRfZGF0YSh1MzIgbW9kZWwsIHN0 cnVjdCBhcm1fc21tdV9kZXZpY2UgKnNtbXUpCj4+ID4+PiAgewo+PiA+Pj4gQEAgLTIwMDEsNiAr MjAyMyw5IEBAIHN0YXRpYyBpbnQgYXJtX3NtbXVfZGV2aWNlX2R0X3Byb2JlKHN0cnVjdCBwbGF0 Zm9ybV9kZXZpY2UgKnBkZXYsCj4+ID4+PiAgICAgICBkYXRhID0gb2ZfZGV2aWNlX2dldF9tYXRj aF9kYXRhKGRldik7Cj4+ID4+PiAgICAgICBzbW11LT52ZXJzaW9uID0gZGF0YS0+dmVyc2lvbjsK Pj4gPj4+ICAgICAgIHNtbXUtPm1vZGVsID0gZGF0YS0+bW9kZWw7Cj4+ID4+PiArICAgICBzbW11 LT5udW1fY2xrcyA9IGRhdGEtPm51bV9jbGtzOwo+PiA+Pj4gKwo+PiA+Pj4gKyAgICAgYXJtX3Nt bXVfZmlsbF9jbGtfZGF0YShzbW11LCBkYXRhLT5jbGtzKTsKPj4gPj4+Cj4+ID4+PiAgICAgICBw YXJzZV9kcml2ZXJfb3B0aW9ucyhzbW11KTsKPj4gPj4+Cj4+ID4+PiBAQCAtMjA5OSw2ICsyMTI0 LDE0IEBAIHN0YXRpYyBpbnQgYXJtX3NtbXVfZGV2aWNlX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9k ZXZpY2UgKnBkZXYpCj4+ID4+PiAgICAgICAgICAgICAgIHNtbXUtPmlycXNbaV0gPSBpcnE7Cj4+ ID4+PiAgICAgICB9Cj4+ID4+Pgo+PiA+Pj4gKyAgICAgZXJyID0gZGV2bV9jbGtfYnVsa19nZXQo c21tdS0+ZGV2LCBzbW11LT5udW1fY2xrcywgc21tdS0+Y2xrcyk7Cj4+ID4+PiArICAgICBpZiAo ZXJyKQo+PiA+Pj4gKyAgICAgICAgICAgICByZXR1cm4gZXJyOwo+PiA+Pj4gKwo+PiA+Pj4gKyAg ICAgZXJyID0gY2xrX2J1bGtfcHJlcGFyZShzbW11LT5udW1fY2xrcywgc21tdS0+Y2xrcyk7Cj4+ ID4+PiArICAgICBpZiAoZXJyKQo+PiA+Pj4gKyAgICAgICAgICAgICByZXR1cm4gZXJyOwo+PiA+ Pj4gKwo+PiA+Pj4gICAgICAgZXJyID0gYXJtX3NtbXVfZGV2aWNlX2NmZ19wcm9iZShzbW11KTsK Pj4gPj4+ICAgICAgIGlmIChlcnIpCj4+ID4+PiAgICAgICAgICAgICAgIHJldHVybiBlcnI7Cj4+ ID4+PiBAQCAtMjE4MSw2ICsyMjE0LDkgQEAgc3RhdGljIGludCBhcm1fc21tdV9kZXZpY2VfcmVt b3ZlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4+ID4+Pgo+PiA+Pj4gICAgICAgLyog VHVybiB0aGUgdGhpbmcgb2ZmICovCj4+ID4+PiAgICAgICB3cml0ZWwoc0NSMF9DTElFTlRQRCwg QVJNX1NNTVVfR1IwX05TKHNtbXUpICsgQVJNX1NNTVVfR1IwX3NDUjApOwo+PiA+Pj4gKwo+PiA+ Pj4gKyAgICAgY2xrX2J1bGtfdW5wcmVwYXJlKHNtbXUtPm51bV9jbGtzLCBzbW11LT5jbGtzKTsK Pj4gPj4+ICsKPj4gPj4+ICAgICAgIHJldHVybiAwOwo+PiA+Pj4gIH0KPj4gPj4+Cj4+ID4+PiBA QCAtMjE5Nyw3ICsyMjMzLDI3IEBAIHN0YXRpYyBpbnQgX19tYXliZV91bnVzZWQgYXJtX3NtbXVf cG1fcmVzdW1lKHN0cnVjdCBkZXZpY2UgKmRldikKPj4gPj4+ICAgICAgIHJldHVybiAwOwo+PiA+ Pj4gIH0KPj4gPj4+Cj4+ID4+PiAtc3RhdGljIFNJTVBMRV9ERVZfUE1fT1BTKGFybV9zbW11X3Bt X29wcywgTlVMTCwgYXJtX3NtbXVfcG1fcmVzdW1lKTsKPj4gPj4+ICtzdGF0aWMgaW50IF9fbWF5 YmVfdW51c2VkIGFybV9zbW11X3J1bnRpbWVfcmVzdW1lKHN0cnVjdCBkZXZpY2UgKmRldikKPj4g Pj4+ICt7Cj4+ID4+PiArICAgICBzdHJ1Y3QgYXJtX3NtbXVfZGV2aWNlICpzbW11ID0gZGV2X2dl dF9kcnZkYXRhKGRldik7Cj4+ID4+PiArCj4+ID4+PiArICAgICByZXR1cm4gY2xrX2J1bGtfZW5h YmxlKHNtbXUtPm51bV9jbGtzLCBzbW11LT5jbGtzKTsKPj4gPj4+ICt9Cj4+ID4+PiArCj4+ID4+ PiArc3RhdGljIGludCBfX21heWJlX3VudXNlZCBhcm1fc21tdV9ydW50aW1lX3N1c3BlbmQoc3Ry dWN0IGRldmljZSAqZGV2KQo+PiA+Pj4gK3sKPj4gPj4+ICsgICAgIHN0cnVjdCBhcm1fc21tdV9k ZXZpY2UgKnNtbXUgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsKPj4gPj4+ICsKPj4gPj4+ICsgICAg IGNsa19idWxrX2Rpc2FibGUoc21tdS0+bnVtX2Nsa3MsIHNtbXUtPmNsa3MpOwo+PiA+Pj4gKwo+ PiA+Pj4gKyAgICAgcmV0dXJuIDA7Cj4+ID4+PiArfQo+PiA+Pj4gKwo+PiA+Pj4gK3N0YXRpYyBj b25zdCBzdHJ1Y3QgZGV2X3BtX29wcyBhcm1fc21tdV9wbV9vcHMgPSB7Cj4+ID4+PiArICAgICBT RVRfU1lTVEVNX1NMRUVQX1BNX09QUyhOVUxMLCBhcm1fc21tdV9wbV9yZXN1bWUpCj4+ID4+Cj4+ ID4+IFRoaXMgaXMgc3VzcGljaW91cy4KPj4gPj4KPj4gPj4gSWYgeW91IG5lZWQgYSBydW50aW1l IHN1c3BlbmQgbWV0aG9kLCB3aHkgZG8geW91IHRoaW5rIHRoYXQgaXQgaXMgbm90IG5lY2Vzc2Fy eQo+PiA+PiB0byBzdXNwZW5kIHRoZSBkZXZpY2UgZHVyaW5nIHN5c3RlbS13aWRlIHRyYW5zaXRp b25zPwo+PiA+Cj4+ID4gT2theSwgc28geW91IHN1Z2dlc3QgdG8gcHV0IGNsb2NrIGRpc2FibGlu ZyBpbiBzYXkgYXJtX3NtbXVfcG1fc3VzcGVuZCgpPwo+PiA+IEluIHRoYXQgY2FzZSB0aGUgY2xv Y2tzIGhhdmUgdG8gYmUgZW5hYmxlZCBpbiB0aGUgcmVzdW1lIHBhdGggdG9vLgo+PiA+Cj4+ID4g SSByZW1lbWJlciBUb21hc3ogcG9pbnRlZCB0byB0aGF0IHdlIHNob3VsZG4ndCBuZWVkIGNsb2Nr IGVuYWJsZSBpbiByZXN1bWUKPj4gPiBwYXRoIFsxXS4KPj4gPgo+PiA+IFsxXSBodHRwczovL2xr bWwub3JnL2xrbWwvMjAxOC8zLzE1LzYwCj4KPiBUaGF0IHdhcyBhbiBhbnN3ZXIgZm9yIGEgZGlm ZmVyZW50IHF1ZXN0aW9uLiBJIGRvbid0IHJlbWVtYmVyCj4gc3VnZ2VzdGluZyBoYXZpbmcgbm8g c3VzcGVuZCBmdW5jdGlvbi4KCk15IGJhZCwgYXBvbG9naWVzLiBZb3UgYXJlIHJpZ2h0LCB3ZSB3 ZXJlIGRpc2N1c3NpbmcgaWYgd2UgbmVlZCBhbnkgYWRkaXRpb25hbApoYW5kbGluZyBvZiBwb3dl ciBmb3IgYXJtX3NtbXVfZGV2aWNlX3Jlc2V0KCkgaW4gYXJtX3NtbXVfcG1fcmVzdW1lKCkuCgo+ IEFsdGhvdWdoLCBnaXZlbiB0aGUgUE0KPiBzdWJzeXN0ZW0gaW50ZXJuYWxzLCB0aGUgc3VzcGVu ZCBmdW5jdGlvbiB3b3VsZG4ndCBiZSBjYWxsZWQgb24gU01NVQo+IGltcGxlbWVudGF0aW9uIG5l ZWRlZCBwb3dlciBjb250cm9sIChzaW5jZSB0aGV5IHdvdWxkIGhhdmUgcnVudGltZSBQTQo+IGVu YWJsZWQpIGFuZCBvbiBvdGhlcnMsIGl0IHdvdWxkIGJlIGNhbGxlZCBidXQgZG8gbm90aGluZyAo c2luY2Ugbm8KPiBjbG9ja3MpLgo+Cj4+Cj4+IEhvbmVzdGx5LCBJIGp1c3QgZG9uJ3Qga25vdy4g Oi0pCj4+Cj4+IEl0IGp1c3QgbG9va3Mgb2RkIHRoZSB3YXkgaXQgaXMgZG9uZS4gIEkgdGhpbmsg dGhlIGNsb2NrIHNob3VsZCBiZQo+PiBnYXRlZCBkdXJpbmcgc3lzdGVtLXdpZGUgc3VzcGVuZCB0 b28sIGJlY2F1c2UgdGhlIHN5c3RlbSBjYW4gc3BlbmQKPj4gbXVjaCBtb3JlIHRpbWUgaW4gYSBz bGVlcCBzdGF0ZSB0aGFuIGluIHRoZSB3b3JraW5nIHN0YXRlLCBvbiBhdmVyYWdlLgo+Pgo+PiBB bmQgbm90ZSB0aGF0IHlvdSBjYW5ub3QgcmVseSBvbiBydW50aW1lIFBNIHRvIGFsd2F5cyBkbyBp dCBmb3IgeW91LAo+PiBiZWNhdXNlIGl0IG1heSBiZSBkaXNhYmxlZCBhdCBhIGNsaWVudCBkZXZp Y2Ugb3IgZXZlbiBibG9ja2VkIGJ5IHVzZXIKPj4gc3BhY2UgdmlhIHBvd2VyL2NvbnRyb2wgaW4g c3lzZnMgYW5kIHRoYXQgc2hvdWxkbid0IG1hdHRlciBmb3IKPj4gc3lzdGVtLXdpZGUgUE0uCj4K PiBVc2VyIHNwYWNlIGJsb2NraW5nIHJ1bnRpbWUgUE0gdGhyb3VnaCBzeXNmcyBpcyBhIGdvb2Qg cG9pbnQuIEknbSBub3QKPiAxMDAlIHN1cmUgaG93IHRoZSBQTSBzdWJzeXN0ZW0gZGVhbHMgd2l0 aCB0aGF0IGluIGNhc2Ugb2Ygc3lzdGVtLXdpZGUKPiBzdXNwZW5kLiBJIGd1ZXNzIGZvciBjb25z aXN0ZW5jeSBhbmQgc2FmZXR5LCB3ZSBzaG91bGQgaGF2ZSB0aGUKPiBzdXNwZW5kIGNhbGxiYWNr LgoKV2lsbCBhZGQgdGhlIGZvbGxvd2luZyBzdXNwZW5kIGNhbGxiYWNrIChzYW1lIGFzIGFybV9z bW11X3J1bnRpbWVfc3VzcGVuZCk6Cgogc3RhdGljIGludCBfX21heWJlX3VudXNlZCBhcm1fc21t dV9wbV9zdXNwZW5kKHN0cnVjdCBkZXZpY2UgKmRldikKIHsKICAgICAgICAgc3RydWN0IGFybV9z bW11X2RldmljZSAqc21tdSA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOwoKICAgICAgICAgY2xrX2J1 bGtfZGlzYWJsZShzbW11LT5udW1fY2xrcywgc21tdS0+Y2xrcyk7CgogICAgICAgICByZXR1cm4g MDsKIH0KCgpCZXN0IHJlZ2FyZHMKVml2ZWsKCj4KPiBCZXN0IHJlZ2FyZHMsCj4gVG9tYXN6Cj4g X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KPiBpb21tdSBt YWlsaW5nIGxpc3QKPiBpb21tdUBsaXN0cy5saW51eC1mb3VuZGF0aW9uLm9yZwo+IGh0dHBzOi8v bGlzdHMubGludXhmb3VuZGF0aW9uLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2lvbW11CgoKCi0tIApR VUFMQ09NTSBJTkRJQSwgb24gYmVoYWxmIG9mIFF1YWxjb21tIElubm92YXRpb24gQ2VudGVyLCBJ bmMuIGlzIGEgbWVtYmVyCm9mIENvZGUgQXVyb3JhIEZvcnVtLCBob3N0ZWQgYnkgVGhlIExpbnV4 IEZvdW5kYXRpb24KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KRnJlZWRyZW5vIG1haWxpbmcgbGlzdApGcmVlZHJlbm9AbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZnJlZWRyZW5v Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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Received: by mail-qk0-f179.google.com with SMTP id d22-v6so15164782qkc.8; Thu, 12 Jul 2018 03:57:26 -0700 (PDT) X-Gm-Message-State: AOUpUlEYHgh4BkOJW/x/CsVD6n9V/CZasfonBxkspRoBDqveQL5r72aw xH6cX4a3o8vN5c8Lf26XQ0BA2FFKPp6B+5g3nO4= X-Google-Smtp-Source: AAOMgpciMDBZwrufQRkH/mYD0rOJcCHW2U1RpmyBUPtnTm+Fs0XDarACjrGrdiWSgg+GrxyqCt2uiAajyCzvaQ31Yyw= X-Received: by 2002:a37:5942:: with SMTP id n63-v6mr1272795qkb.28.1531393046282; Thu, 12 Jul 2018 03:57:26 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:ac8:1082:0:0:0:0:0 with HTTP; Thu, 12 Jul 2018 03:57:25 -0700 (PDT) In-Reply-To: References: <20180708173413.1965-1-vivek.gautam@codeaurora.org> <20180708173413.1965-2-vivek.gautam@codeaurora.org> <17407514.unFVTGoGrn@aspire.rjw.lan> From: Vivek Gautam Date: Thu, 12 Jul 2018 16:27:25 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v12 1/4] iommu/arm-smmu: Add pm_runtime/sleep ops To: Tomasz Figa Cc: "Rafael J. Wysocki" , Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux PM , sboyd@kernel.org, Will Deacon , "Rafael J. Wysocki" , Linux Kernel Mailing List , "list@263.net:IOMMU DRIVERS , Joerg Roedel ," , Rob Herring , linux-arm-msm , freedreno Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, Jul 11, 2018 at 6:21 PM, Tomasz Figa wrote: > On Wed, Jul 11, 2018 at 8:11 PM Rafael J. Wysocki wrote: >> >> On Wed, Jul 11, 2018 at 12:55 PM, Vivek Gautam >> wrote: >> > Hi Rafael, >> > >> > >> > On Wed, Jul 11, 2018 at 3:20 PM, Rafael J. Wysocki wrote: >> >> On Sunday, July 8, 2018 7:34:10 PM CEST Vivek Gautam wrote: >> >>> From: Sricharan R >> >>> >> >>> The smmu needs to be functional only when the respective >> >>> master's using it are active. The device_link feature >> >>> helps to track such functional dependencies, so that the >> >>> iommu gets powered when the master device enables itself >> >>> using pm_runtime. So by adapting the smmu driver for >> >>> runtime pm, above said dependency can be addressed. >> >>> >> >>> This patch adds the pm runtime/sleep callbacks to the >> >>> driver and also the functions to parse the smmu clocks >> >>> from DT and enable them in resume/suspend. >> >>> >> >>> Signed-off-by: Sricharan R >> >>> Signed-off-by: Archit Taneja >> >>> [vivek: Clock rework to request bulk of clocks] >> >>> Signed-off-by: Vivek Gautam >> >>> Reviewed-by: Tomasz Figa >> >>> --- >> >>> >> >>> - No change since v11. >> >>> >> >>> drivers/iommu/arm-smmu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++-- >> >>> 1 file changed, 58 insertions(+), 2 deletions(-) >> >>> >> >>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c >> >>> index f7a96bcf94a6..a01d0dde21dd 100644 >> >>> --- a/drivers/iommu/arm-smmu.c >> >>> +++ b/drivers/iommu/arm-smmu.c >> >>> @@ -48,6 +48,7 @@ >> >>> #include >> >>> #include >> >>> #include >> >>> +#include >> >>> #include >> >>> #include >> >>> >> >>> @@ -205,6 +206,8 @@ struct arm_smmu_device { >> >>> u32 num_global_irqs; >> >>> u32 num_context_irqs; >> >>> unsigned int *irqs; >> >>> + struct clk_bulk_data *clks; >> >>> + int num_clks; >> >>> >> >>> u32 cavium_id_base; /* Specific to Cavium */ >> >>> >> >>> @@ -1897,10 +1900,12 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) >> >>> struct arm_smmu_match_data { >> >>> enum arm_smmu_arch_version version; >> >>> enum arm_smmu_implementation model; >> >>> + const char * const *clks; >> >>> + int num_clks; >> >>> }; >> >>> >> >>> #define ARM_SMMU_MATCH_DATA(name, ver, imp) \ >> >>> -static struct arm_smmu_match_data name = { .version = ver, .model = imp } >> >>> +static const struct arm_smmu_match_data name = { .version = ver, .model = imp } >> >>> >> >>> ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU); >> >>> ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU); >> >>> @@ -1919,6 +1924,23 @@ static const struct of_device_id arm_smmu_of_match[] = { >> >>> }; >> >>> MODULE_DEVICE_TABLE(of, arm_smmu_of_match); >> >>> >> >>> +static void arm_smmu_fill_clk_data(struct arm_smmu_device *smmu, >> >>> + const char * const *clks) >> >>> +{ >> >>> + int i; >> >>> + >> >>> + if (smmu->num_clks < 1) >> >>> + return; >> >>> + >> >>> + smmu->clks = devm_kcalloc(smmu->dev, smmu->num_clks, >> >>> + sizeof(*smmu->clks), GFP_KERNEL); >> >>> + if (!smmu->clks) >> >>> + return; >> >>> + >> >>> + for (i = 0; i < smmu->num_clks; i++) >> >>> + smmu->clks[i].id = clks[i]; >> >>> +} >> >>> + >> >>> #ifdef CONFIG_ACPI >> >>> static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu) >> >>> { >> >>> @@ -2001,6 +2023,9 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, >> >>> data = of_device_get_match_data(dev); >> >>> smmu->version = data->version; >> >>> smmu->model = data->model; >> >>> + smmu->num_clks = data->num_clks; >> >>> + >> >>> + arm_smmu_fill_clk_data(smmu, data->clks); >> >>> >> >>> parse_driver_options(smmu); >> >>> >> >>> @@ -2099,6 +2124,14 @@ static int arm_smmu_device_probe(struct platform_device *pdev) >> >>> smmu->irqs[i] = irq; >> >>> } >> >>> >> >>> + err = devm_clk_bulk_get(smmu->dev, smmu->num_clks, smmu->clks); >> >>> + if (err) >> >>> + return err; >> >>> + >> >>> + err = clk_bulk_prepare(smmu->num_clks, smmu->clks); >> >>> + if (err) >> >>> + return err; >> >>> + >> >>> err = arm_smmu_device_cfg_probe(smmu); >> >>> if (err) >> >>> return err; >> >>> @@ -2181,6 +2214,9 @@ static int arm_smmu_device_remove(struct platform_device *pdev) >> >>> >> >>> /* Turn the thing off */ >> >>> writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); >> >>> + >> >>> + clk_bulk_unprepare(smmu->num_clks, smmu->clks); >> >>> + >> >>> return 0; >> >>> } >> >>> >> >>> @@ -2197,7 +2233,27 @@ static int __maybe_unused arm_smmu_pm_resume(struct device *dev) >> >>> return 0; >> >>> } >> >>> >> >>> -static SIMPLE_DEV_PM_OPS(arm_smmu_pm_ops, NULL, arm_smmu_pm_resume); >> >>> +static int __maybe_unused arm_smmu_runtime_resume(struct device *dev) >> >>> +{ >> >>> + struct arm_smmu_device *smmu = dev_get_drvdata(dev); >> >>> + >> >>> + return clk_bulk_enable(smmu->num_clks, smmu->clks); >> >>> +} >> >>> + >> >>> +static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) >> >>> +{ >> >>> + struct arm_smmu_device *smmu = dev_get_drvdata(dev); >> >>> + >> >>> + clk_bulk_disable(smmu->num_clks, smmu->clks); >> >>> + >> >>> + return 0; >> >>> +} >> >>> + >> >>> +static const struct dev_pm_ops arm_smmu_pm_ops = { >> >>> + SET_SYSTEM_SLEEP_PM_OPS(NULL, arm_smmu_pm_resume) >> >> >> >> This is suspicious. >> >> >> >> If you need a runtime suspend method, why do you think that it is not necessary >> >> to suspend the device during system-wide transitions? >> > >> > Okay, so you suggest to put clock disabling in say arm_smmu_pm_suspend()? >> > In that case the clocks have to be enabled in the resume path too. >> > >> > I remember Tomasz pointed to that we shouldn't need clock enable in resume >> > path [1]. >> > >> > [1] https://lkml.org/lkml/2018/3/15/60 > > That was an answer for a different question. I don't remember > suggesting having no suspend function. My bad, apologies. You are right, we were discussing if we need any additional handling of power for arm_smmu_device_reset() in arm_smmu_pm_resume(). > Although, given the PM > subsystem internals, the suspend function wouldn't be called on SMMU > implementation needed power control (since they would have runtime PM > enabled) and on others, it would be called but do nothing (since no > clocks). > >> >> Honestly, I just don't know. :-) >> >> It just looks odd the way it is done. I think the clock should be >> gated during system-wide suspend too, because the system can spend >> much more time in a sleep state than in the working state, on average. >> >> And note that you cannot rely on runtime PM to always do it for you, >> because it may be disabled at a client device or even blocked by user >> space via power/control in sysfs and that shouldn't matter for >> system-wide PM. > > User space blocking runtime PM through sysfs is a good point. I'm not > 100% sure how the PM subsystem deals with that in case of system-wide > suspend. I guess for consistency and safety, we should have the > suspend callback. Will add the following suspend callback (same as arm_smmu_runtime_suspend): static int __maybe_unused arm_smmu_pm_suspend(struct device *dev) { struct arm_smmu_device *smmu = dev_get_drvdata(dev); clk_bulk_disable(smmu->num_clks, smmu->clks); return 0; } Best regards Vivek > > Best regards, > Tomasz > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation