From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vivek Gautam Subject: Re: [PATCH v2 3/4] dt-bindings: phy: Add support for QMP phy Date: Mon, 12 Dec 2016 22:10:36 +0530 Message-ID: References: <1479816163-5260-1-git-send-email-vivek.gautam@codeaurora.org> <1479816163-5260-4-git-send-email-vivek.gautam@codeaurora.org> <20161128225543.GM6095@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <20161128225543.GM6095-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Stephen Boyd Cc: kishon , robh+dt , Mark Rutland , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Srinivas Kandagatla , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org Hi Stephen, On Tue, Nov 29, 2016 at 4:25 AM, Stephen Boyd wrote: > On 11/22, Vivek Gautam wrote: >> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt >> new file mode 100644 >> index 0000000..ffb173b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt >> @@ -0,0 +1,74 @@ >> +Qualcomm QMP PHY >> +---------------- >> + >> +QMP phy controller supports physical layer functionality for a number of >> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. >> + >> +Required properties: >> + - compatible: compatible list, contains: >> + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, >> + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. >> + - reg: list of offset and length pair of the PHY register sets. >> + at index 0: offset and length of register set for PHY common >> + serdes block. >> + from index 1 - N: offset and length of register set for each lane, >> + for N number of phy lanes (ports). >> + - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes. >> + - #phy-cells: must be 1 >> + - Cell after phy phandle should be the port (lane) number. >> + - clocks: a list of phandles and clock-specifier pairs, >> + one for each entry in clock-names. >> + - clock-names: must be "cfg_ahb" for phy config clock, >> + "aux" for phy aux clock, >> + "ref_clk" for 19.2 MHz ref clk, >> + "ref_clk_src" for reference clock source, > > We typically leave "clk" out of clk names because it's redundant. > >> + "pipe" for pipe clock specific to >> + each port/lane (Optional). > > The pipe clocks are orphaned right now. We should add an output > clock from the phy to go into the controller and back into the > phy if I recall correctly. The phy should be a clock provider > itself so it can output the pipe clock source into GCC and back > into the phy and controller. You are correct. The pipe clocks come out of PHY controllers and go back to the gcc that gates them finally. I will register the phy drivers as clock providers so that gcc can make reference to it. Best Regards Vivek -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753035AbcLLQkm (ORCPT ); Mon, 12 Dec 2016 11:40:42 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:57378 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752100AbcLLQkk (ORCPT ); Mon, 12 Dec 2016 11:40:40 -0500 DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 464606146A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=vivek.gautam@codeaurora.org MIME-Version: 1.0 In-Reply-To: <20161128225543.GM6095@codeaurora.org> References: <1479816163-5260-1-git-send-email-vivek.gautam@codeaurora.org> <1479816163-5260-4-git-send-email-vivek.gautam@codeaurora.org> <20161128225543.GM6095@codeaurora.org> From: Vivek Gautam Date: Mon, 12 Dec 2016 22:10:36 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 3/4] dt-bindings: phy: Add support for QMP phy To: Stephen Boyd Cc: kishon , "robh+dt" , Mark Rutland , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stephen, On Tue, Nov 29, 2016 at 4:25 AM, Stephen Boyd wrote: > On 11/22, Vivek Gautam wrote: >> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt >> new file mode 100644 >> index 0000000..ffb173b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt >> @@ -0,0 +1,74 @@ >> +Qualcomm QMP PHY >> +---------------- >> + >> +QMP phy controller supports physical layer functionality for a number of >> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. >> + >> +Required properties: >> + - compatible: compatible list, contains: >> + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, >> + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. >> + - reg: list of offset and length pair of the PHY register sets. >> + at index 0: offset and length of register set for PHY common >> + serdes block. >> + from index 1 - N: offset and length of register set for each lane, >> + for N number of phy lanes (ports). >> + - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes. >> + - #phy-cells: must be 1 >> + - Cell after phy phandle should be the port (lane) number. >> + - clocks: a list of phandles and clock-specifier pairs, >> + one for each entry in clock-names. >> + - clock-names: must be "cfg_ahb" for phy config clock, >> + "aux" for phy aux clock, >> + "ref_clk" for 19.2 MHz ref clk, >> + "ref_clk_src" for reference clock source, > > We typically leave "clk" out of clk names because it's redundant. > >> + "pipe" for pipe clock specific to >> + each port/lane (Optional). > > The pipe clocks are orphaned right now. We should add an output > clock from the phy to go into the controller and back into the > phy if I recall correctly. The phy should be a clock provider > itself so it can output the pipe clock source into GCC and back > into the phy and controller. You are correct. The pipe clocks come out of PHY controllers and go back to the gcc that gates them finally. I will register the phy drivers as clock providers so that gcc can make reference to it. Best Regards Vivek -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project