From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751607AbdB0R2Y (ORCPT ); Mon, 27 Feb 2017 12:28:24 -0500 Received: from mail-io0-f193.google.com ([209.85.223.193]:33290 "EHLO mail-io0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751291AbdB0R14 (ORCPT ); Mon, 27 Feb 2017 12:27:56 -0500 MIME-Version: 1.0 In-Reply-To: <1473473748-22331-3-git-send-email-zyw@rock-chips.com> References: <1473473748-22331-1-git-send-email-zyw@rock-chips.com> <1473473748-22331-3-git-send-email-zyw@rock-chips.com> From: Enric Balletbo Serra Date: Mon, 27 Feb 2017 18:27:19 +0100 Message-ID: Subject: Re: [PATCH v15 2/5] Documentation: bindings: add dt documentation for cdn DP controller To: Chris Zhong Cc: Doug Anderson , tfiga@chromium.org, =?UTF-8?Q?Heiko_St=C3=BCbner?= , yzq@rock-chips.com, Guenter Roeck , myungjoo.ham@samsung.com, cw00.choi@samsung.com, wulf@rock-chips.com, marcheu@chromium.org, Brian Norris , zhengxing@rock-chips.com, cychiang@chromium.org, hychao@chromium.org, Mark Brown , linux-rockchip@lists.infradead.org, "devicetree@vger.kernel.org" , Kumar Gala , linux-kernel , Ian Campbell , Rob Herring , Pawel Moll , Mark Rutland , "linux-arm-kernel@lists.infradead.org" , mark.yao@rock-chips.com Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, 2016-09-10 4:15 GMT+02:00 Chris Zhong : > This patch adds a binding that describes the cdn DP controller for > rk3399. > > Signed-off-by: Chris Zhong > Acked-by: Rob Herring > Reviewed-by: Guenter Roeck > > --- > > Changes in v15: None > Changes in v14: None > Changes in v13: > - add dptx and apb reset > > Changes in v12: None > Changes in v11: > - refer dp phy > > Changes in v10: > - add pclk_vio_grf clock > > Changes in v9: > - modify the reference phy = <&tcphy0 0>, <&tcphy1 0>; > > Changes in v8: None > Changes in v7: None > Changes in v6: > - add assigned-clocks and assigned-clock-rates > - add power-domains > > Changes in v5: None > Changes in v4: > - add a reset node > - support 2 phys > > Changes in v3: > - add SoC specific compatible string > - remove reg = <1>; > > Changes in v2: None > Changes in v1: > - add extcon node description > - add #sound-dai-cells description > > .../bindings/display/rockchip/cdn-dp-rockchip.txt | 75 ++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > > diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > new file mode 100644 > index 0000000..9bd2c13 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > @@ -0,0 +1,75 @@ > +Rockchip RK3399 specific extensions to the cdn Display Port > +================================ > + > +Required properties: > +- compatible: must be "rockchip,rk3399-cdn-dp" > + > +- reg: physical base address of the controller and length > + > +- clocks: from common clock binding: handle to dp clock. > + > +- clock-names: from common clock binding: > + Required elements: "core-clk" "pclk" "spdif" "grf" > + > +- resets : a list of phandle + reset specifier pairs > +- reset-names : string reset name, must be: > + "spdif", "dptx", "apb". > +- power-domains : power-domain property defined with a phandle > + to respective power domain. > +- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> > +- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 > + > +- rockchip,grf: this soc should set GRF regs, so need get grf here. > + > +- ports: contain a port nodes with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + contained 2 endpoints, connecting to the output of vop. > + > +- phys: from general PHY binding: the phandle for the PHY device. > + > +- extcon: extcon specifier for the Power Delivery > + > +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF > + > +------------------------------------------------------------------------------- > + > +Example: > + cdn_dp: dp@fec00000 { > + compatible = "rockchip,rk3399-cdn-dp"; > + reg = <0x0 0xfec00000 0x0 0x100000>; > + interrupts = ; > + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, > + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; > + clock-names = "core-clk", "pclk", "spdif", "grf"; > + assigned-clocks = <&cru SCLK_DP_CORE>; > + assigned-clock-rates = <100000000>; > + power-domains = <&power RK3399_PD_HDCP>; > + phys = <&tcphy0_dp>, <&tcphy1_dp>; > + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, > + <&cru SRST_P_UPHY0_APB>; > + reset-names = "spdif", "dptx", "apb"; > + extcon = <&fusb0>, <&fusb1>; > + rockchip,grf = <&grf>; > + #address-cells = <1>; > + #size-cells = <0>; > + #sound-dai-cells = <1>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + dp_in: port { > + #address-cells = <1>; > + #size-cells = <0>; > + dp_in_vopb: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&vopb_out_dp>; > + }; > + > + dp_in_vopl: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&vopl_out_dp>; > + }; > + }; > + }; > + }; > -- > 1.9.1 > CC'ing Mark Yao I saw that the cdn-dp driver is merged but not the documentation binding. Maybe we forget to include this patch with the pull request? Or there is another reason? Thanks, Enric From mboxrd@z Thu Jan 1 00:00:00 1970 From: Enric Balletbo Serra Subject: Re: [PATCH v15 2/5] Documentation: bindings: add dt documentation for cdn DP controller Date: Mon, 27 Feb 2017 18:27:19 +0100 Message-ID: References: <1473473748-22331-1-git-send-email-zyw@rock-chips.com> <1473473748-22331-3-git-send-email-zyw@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1473473748-22331-3-git-send-email-zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Chris Zhong Cc: Mark Rutland , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Doug Anderson , wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org, Guenter Roeck , hychao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, cychiang-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org, cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, Brian Norris , linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Pawel Moll , Ian Campbell , yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org, Mark Brown , marcheu-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org, linux-kernel , tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, Rob Herring , Kumar Gala List-Id: devicetree@vger.kernel.org Hi all, 2016-09-10 4:15 GMT+02:00 Chris Zhong : > This patch adds a binding that describes the cdn DP controller for > rk3399. > > Signed-off-by: Chris Zhong > Acked-by: Rob Herring > Reviewed-by: Guenter Roeck > > --- > > Changes in v15: None > Changes in v14: None > Changes in v13: > - add dptx and apb reset > > Changes in v12: None > Changes in v11: > - refer dp phy > > Changes in v10: > - add pclk_vio_grf clock > > Changes in v9: > - modify the reference phy = <&tcphy0 0>, <&tcphy1 0>; > > Changes in v8: None > Changes in v7: None > Changes in v6: > - add assigned-clocks and assigned-clock-rates > - add power-domains > > Changes in v5: None > Changes in v4: > - add a reset node > - support 2 phys > > Changes in v3: > - add SoC specific compatible string > - remove reg = <1>; > > Changes in v2: None > Changes in v1: > - add extcon node description > - add #sound-dai-cells description > > .../bindings/display/rockchip/cdn-dp-rockchip.txt | 75 ++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > > diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > new file mode 100644 > index 0000000..9bd2c13 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > @@ -0,0 +1,75 @@ > +Rockchip RK3399 specific extensions to the cdn Display Port > +================================ > + > +Required properties: > +- compatible: must be "rockchip,rk3399-cdn-dp" > + > +- reg: physical base address of the controller and length > + > +- clocks: from common clock binding: handle to dp clock. > + > +- clock-names: from common clock binding: > + Required elements: "core-clk" "pclk" "spdif" "grf" > + > +- resets : a list of phandle + reset specifier pairs > +- reset-names : string reset name, must be: > + "spdif", "dptx", "apb". > +- power-domains : power-domain property defined with a phandle > + to respective power domain. > +- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> > +- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 > + > +- rockchip,grf: this soc should set GRF regs, so need get grf here. > + > +- ports: contain a port nodes with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + contained 2 endpoints, connecting to the output of vop. > + > +- phys: from general PHY binding: the phandle for the PHY device. > + > +- extcon: extcon specifier for the Power Delivery > + > +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF > + > +------------------------------------------------------------------------------- > + > +Example: > + cdn_dp: dp@fec00000 { > + compatible = "rockchip,rk3399-cdn-dp"; > + reg = <0x0 0xfec00000 0x0 0x100000>; > + interrupts = ; > + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, > + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; > + clock-names = "core-clk", "pclk", "spdif", "grf"; > + assigned-clocks = <&cru SCLK_DP_CORE>; > + assigned-clock-rates = <100000000>; > + power-domains = <&power RK3399_PD_HDCP>; > + phys = <&tcphy0_dp>, <&tcphy1_dp>; > + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, > + <&cru SRST_P_UPHY0_APB>; > + reset-names = "spdif", "dptx", "apb"; > + extcon = <&fusb0>, <&fusb1>; > + rockchip,grf = <&grf>; > + #address-cells = <1>; > + #size-cells = <0>; > + #sound-dai-cells = <1>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + dp_in: port { > + #address-cells = <1>; > + #size-cells = <0>; > + dp_in_vopb: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&vopb_out_dp>; > + }; > + > + dp_in_vopl: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&vopl_out_dp>; > + }; > + }; > + }; > + }; > -- > 1.9.1 > CC'ing Mark Yao I saw that the cdn-dp driver is merged but not the documentation binding. Maybe we forget to include this patch with the pull request? Or there is another reason? Thanks, Enric From mboxrd@z Thu Jan 1 00:00:00 1970 From: eballetbo@gmail.com (Enric Balletbo Serra) Date: Mon, 27 Feb 2017 18:27:19 +0100 Subject: [PATCH v15 2/5] Documentation: bindings: add dt documentation for cdn DP controller In-Reply-To: <1473473748-22331-3-git-send-email-zyw@rock-chips.com> References: <1473473748-22331-1-git-send-email-zyw@rock-chips.com> <1473473748-22331-3-git-send-email-zyw@rock-chips.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi all, 2016-09-10 4:15 GMT+02:00 Chris Zhong : > This patch adds a binding that describes the cdn DP controller for > rk3399. > > Signed-off-by: Chris Zhong > Acked-by: Rob Herring > Reviewed-by: Guenter Roeck > > --- > > Changes in v15: None > Changes in v14: None > Changes in v13: > - add dptx and apb reset > > Changes in v12: None > Changes in v11: > - refer dp phy > > Changes in v10: > - add pclk_vio_grf clock > > Changes in v9: > - modify the reference phy = <&tcphy0 0>, <&tcphy1 0>; > > Changes in v8: None > Changes in v7: None > Changes in v6: > - add assigned-clocks and assigned-clock-rates > - add power-domains > > Changes in v5: None > Changes in v4: > - add a reset node > - support 2 phys > > Changes in v3: > - add SoC specific compatible string > - remove reg = <1>; > > Changes in v2: None > Changes in v1: > - add extcon node description > - add #sound-dai-cells description > > .../bindings/display/rockchip/cdn-dp-rockchip.txt | 75 ++++++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > > diff --git a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > new file mode 100644 > index 0000000..9bd2c13 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt > @@ -0,0 +1,75 @@ > +Rockchip RK3399 specific extensions to the cdn Display Port > +================================ > + > +Required properties: > +- compatible: must be "rockchip,rk3399-cdn-dp" > + > +- reg: physical base address of the controller and length > + > +- clocks: from common clock binding: handle to dp clock. > + > +- clock-names: from common clock binding: > + Required elements: "core-clk" "pclk" "spdif" "grf" > + > +- resets : a list of phandle + reset specifier pairs > +- reset-names : string reset name, must be: > + "spdif", "dptx", "apb". > +- power-domains : power-domain property defined with a phandle > + to respective power domain. > +- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> > +- assigned-clock-rates : the DP core clk frequency, shall be: 100000000 > + > +- rockchip,grf: this soc should set GRF regs, so need get grf here. > + > +- ports: contain a port nodes with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + contained 2 endpoints, connecting to the output of vop. > + > +- phys: from general PHY binding: the phandle for the PHY device. > + > +- extcon: extcon specifier for the Power Delivery > + > +- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF > + > +------------------------------------------------------------------------------- > + > +Example: > + cdn_dp: dp at fec00000 { > + compatible = "rockchip,rk3399-cdn-dp"; > + reg = <0x0 0xfec00000 0x0 0x100000>; > + interrupts = ; > + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, > + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; > + clock-names = "core-clk", "pclk", "spdif", "grf"; > + assigned-clocks = <&cru SCLK_DP_CORE>; > + assigned-clock-rates = <100000000>; > + power-domains = <&power RK3399_PD_HDCP>; > + phys = <&tcphy0_dp>, <&tcphy1_dp>; > + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, > + <&cru SRST_P_UPHY0_APB>; > + reset-names = "spdif", "dptx", "apb"; > + extcon = <&fusb0>, <&fusb1>; > + rockchip,grf = <&grf>; > + #address-cells = <1>; > + #size-cells = <0>; > + #sound-dai-cells = <1>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + dp_in: port { > + #address-cells = <1>; > + #size-cells = <0>; > + dp_in_vopb: endpoint at 0 { > + reg = <0>; > + remote-endpoint = <&vopb_out_dp>; > + }; > + > + dp_in_vopl: endpoint at 1 { > + reg = <1>; > + remote-endpoint = <&vopl_out_dp>; > + }; > + }; > + }; > + }; > -- > 1.9.1 > CC'ing Mark Yao I saw that the cdn-dp driver is merged but not the documentation binding. Maybe we forget to include this patch with the pull request? Or there is another reason? Thanks, Enric