From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87332C433F5 for ; Wed, 15 Sep 2021 09:07:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FC4061101 for ; Wed, 15 Sep 2021 09:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231926AbhIOJIX (ORCPT ); Wed, 15 Sep 2021 05:08:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231875AbhIOJIW (ORCPT ); Wed, 15 Sep 2021 05:08:22 -0400 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19709C061574 for ; Wed, 15 Sep 2021 02:07:04 -0700 (PDT) Received: by mail-qk1-x733.google.com with SMTP id y144so2653469qkb.6 for ; Wed, 15 Sep 2021 02:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=0RJdDy9GciodUDReXjUDaIDFkjFGW73S7dZ7n74WMu8=; b=YILCy+h7tFJaAsVRaaAIlQKJYokPpV55xGBcCthglwybJ0Gzzkh/Kwywtit4p6DlbG c2H5KZM3i/9FqennjeteKBG2nu0lBhbaGvVLnsAB6b5VT8AAxLpXDZKhIgeNUA5sfc+S IsyX3TKqaXRSdaqOecKGcV80HxeTx+NegIPkI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0RJdDy9GciodUDReXjUDaIDFkjFGW73S7dZ7n74WMu8=; b=Cxk4ovfgxnu5s9SRy9TK+MJzz1NiuT5kK5bgKL5icbTeF7t5/P0+dQOwC7eaIz2C5s 71ksDP/1dzyANwuxf+3GarqR84LET++RQysY5YF/NOILw0057Qy8amiUzanUPGw5vjZY I3fxAPQh3kwyTiYs2Q8D2ZWcC8XfLn1bKdwe6HJYJ4QQ6bboMImAPZS1HyEPfuITZYlM VM3LxIzxky8iRrT4VivzobWtyF78/5dyCgT2xXJbsCBHdt6l3VfM2uVL5pZuOOJNPiRD KmR8E7+zHZST0OjUBEGLNqd51B2kOp6bUzZYYALIyAIngqvg0xI32KYaDRKMuVUORiF0 K5dw== X-Gm-Message-State: AOAM530egWAEmepr8FhcodlxqFLkoulDYtvAix1p1Ae39kjHnGb60lik b5fFI7yq4GwV7nfZYM80Ywvq5xUtc3a0FMNssiVJmw== X-Google-Smtp-Source: ABdhPJws1Ho/iB+xb+WL3xHvw7qxPAcEuT6fJ2i6E7ObmyaGC6uVnXaezCAoFfxaSUWTEFxDkjgiHEAfQ2mE9qxVyHg= X-Received: by 2002:a05:620a:4495:: with SMTP id x21mr8855230qkp.378.1631696823227; Wed, 15 Sep 2021 02:07:03 -0700 (PDT) MIME-Version: 1.0 References: <20210914100415.1549208-1-daniel@0x0f.com> In-Reply-To: From: Daniel Palmer Date: Wed, 15 Sep 2021 18:06:52 +0900 Message-ID: Subject: Re: [PATCH 0/3] SigmaStar SSD20XD GPIO interrupt controller To: Andrew Lunn Cc: DTML , Rob Herring , Marc Zyngier , Thomas Gleixner , linux-arm-kernel , Romain Perier Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Andrew, On Wed, 15 Sept 2021 at 00:59, Andrew Lunn wrote: > How are the GPIOs mapped to the interrupts? Is it a simple 1:1? Unfortunately, no. I wanted to add the GPIO controller part of this to this same series but there are some patches in flight for that so it would have been messy. You can see that here though: https://github.com/linux-chenxing/linux/commit/88345dc470bf07d36aa1ddab09551ed33a1cfb22 They've really made a mess of this. Their whole GPIO thing is a mess with no clear logic between the pin names and the register locations etc. This IRQ part is no exception. IRQ 0 from this thing isn't for the pin called GPIO0 or anything sane like that. > The GPIO core has some support for the GPIO drivers to be also > interrupt controllers. So if this interrupt control is dedicated to > GPIO, you would be better to make it part of the GPIO driver. I don't think so. One reason is the non-linear mapping stuff. A second reason is this GPIO interrupt controller might handle GPIO interrupts for multiple GPIO controller blocks. Finally, in newer chips they've replaced one of the GPIO blocks with a new IP which will need it's own driver. That GPIO controller still seems to use this same IRQ block to handle it's interrupts. So if this code is wrapped into the GPIO driver itself it would end up duplicated in two GPIO drivers. Cheers, Daniel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4E1EC433F5 for ; Wed, 15 Sep 2021 09:09:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7807F61244 for ; Wed, 15 Sep 2021 09:09:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7807F61244 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IuXgrcP13Uuu2hANJbABiHUtojTMvIwoOlh37uB+744=; b=aozhqRJoD9uN+H ruQ5WSmJaDoxLDAXKMH/PDE4yxSFWw/Hj3FlbLzHMdnCPr2XEHgJhPxq7m2agdQO6WRA1NLclj+k1 JOJUt9Ng5c2LEbCjFSUe3IlKt114om0bNpDHllsxSf2N0udAtUDJ75afjdh809zax6sAk/xMcoyJp 3+Ra8x8n4hOo/gXg6cl0oBn/QOshMYuSs2nTBVFb0XU9tnOqwRzsiybW5AXLtU/cdqqTqlMitnDRH wwWi6kDmUDT8pg4ygBzPZhLf01PSW/+3UU5HMMmYqbfE0Ocz0h06seSvwjk26UApAYBza5WM9kmN+ gWe6f5iAbt98emt9d+Vw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mQQsq-008bEE-1Y; Wed, 15 Sep 2021 09:07:12 +0000 Received: from mail-qk1-x736.google.com ([2607:f8b0:4864:20::736]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mQQsj-008bCT-3Y for linux-arm-kernel@lists.infradead.org; Wed, 15 Sep 2021 09:07:06 +0000 Received: by mail-qk1-x736.google.com with SMTP id f22so2662099qkm.5 for ; Wed, 15 Sep 2021 02:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=0RJdDy9GciodUDReXjUDaIDFkjFGW73S7dZ7n74WMu8=; b=YILCy+h7tFJaAsVRaaAIlQKJYokPpV55xGBcCthglwybJ0Gzzkh/Kwywtit4p6DlbG c2H5KZM3i/9FqennjeteKBG2nu0lBhbaGvVLnsAB6b5VT8AAxLpXDZKhIgeNUA5sfc+S IsyX3TKqaXRSdaqOecKGcV80HxeTx+NegIPkI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0RJdDy9GciodUDReXjUDaIDFkjFGW73S7dZ7n74WMu8=; b=3Xd+OWV7ori1UvnhX3o0pM8FE+mvD8MQUHzRfrKXC8P7OgRPqpCRKBp73+lwDvWMKD uhHblONGghj11uzefqIeBqKjuvxFPjkI02UCh7E+iTvCXCa1ZEd6/XI7Lvc88hRf80I+ nAzP0xWc/QO64cm0HBa5PX3+1Q9csssllWNZmJAoce0uZ2tiCvZex85FOd3+cNPHpGHh mKNWrjusEYaGxkpOtjv+9Ol87V7sP6953R+9Qco4ar1vPbnZmtH+YM+zMqqUydsjGxDy aRqGgzVp2dNFkw6fPKzu02h4spj3y/hc8PXHIKx8bRHpv6eoUZvYXAkQ8csroDdSdwqE F5XA== X-Gm-Message-State: AOAM530hCuZTGueFk05l6Pj/ZWpgoZ3ySPoaX55hmminD7HqwvAJ+xQA 1hWAKnVqph6wqbl7lsCI+ld3SPLqx/fmSJyVGdj3qw== X-Google-Smtp-Source: ABdhPJws1Ho/iB+xb+WL3xHvw7qxPAcEuT6fJ2i6E7ObmyaGC6uVnXaezCAoFfxaSUWTEFxDkjgiHEAfQ2mE9qxVyHg= X-Received: by 2002:a05:620a:4495:: with SMTP id x21mr8855230qkp.378.1631696823227; Wed, 15 Sep 2021 02:07:03 -0700 (PDT) MIME-Version: 1.0 References: <20210914100415.1549208-1-daniel@0x0f.com> In-Reply-To: From: Daniel Palmer Date: Wed, 15 Sep 2021 18:06:52 +0900 Message-ID: Subject: Re: [PATCH 0/3] SigmaStar SSD20XD GPIO interrupt controller To: Andrew Lunn Cc: DTML , Rob Herring , Marc Zyngier , Thomas Gleixner , linux-arm-kernel , Romain Perier X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210915_020705_346190_96EE8271 X-CRM114-Status: GOOD ( 16.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Andrew, On Wed, 15 Sept 2021 at 00:59, Andrew Lunn wrote: > How are the GPIOs mapped to the interrupts? Is it a simple 1:1? Unfortunately, no. I wanted to add the GPIO controller part of this to this same series but there are some patches in flight for that so it would have been messy. You can see that here though: https://github.com/linux-chenxing/linux/commit/88345dc470bf07d36aa1ddab09551ed33a1cfb22 They've really made a mess of this. Their whole GPIO thing is a mess with no clear logic between the pin names and the register locations etc. This IRQ part is no exception. IRQ 0 from this thing isn't for the pin called GPIO0 or anything sane like that. > The GPIO core has some support for the GPIO drivers to be also > interrupt controllers. So if this interrupt control is dedicated to > GPIO, you would be better to make it part of the GPIO driver. I don't think so. One reason is the non-linear mapping stuff. A second reason is this GPIO interrupt controller might handle GPIO interrupts for multiple GPIO controller blocks. Finally, in newer chips they've replaced one of the GPIO blocks with a new IP which will need it's own driver. That GPIO controller still seems to use this same IRQ block to handle it's interrupts. So if this code is wrapped into the GPIO driver itself it would end up duplicated in two GPIO drivers. Cheers, Daniel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel