From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Peter_Fr=C3=BChberger?= Subject: Re: [PATCH v4 1/2] drm/i915/dp: Enable DP audio stall fix for gen9 platforms Date: Wed, 4 Jan 2017 10:11:41 +0100 Message-ID: References: <1477442271.19344.41.camel@dk-H97M-D3H> <1477449456-22146-1-git-send-email-dhinakaran.pandiyan@intel.com> <87vaw3gsav.fsf@intel.com> <1478285685.16546.4.camel@dk-H97M-D3H> <87wpghiul4.fsf@intel.com> <1478392821.16546.28.camel@dk-H97M-D3H> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0225253141==" Return-path: Received: from mail-io0-x243.google.com (mail-io0-x243.google.com [IPv6:2607:f8b0:4001:c06::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB09E89930 for ; Wed, 4 Jan 2017 09:11:42 +0000 (UTC) Received: by mail-io0-x243.google.com with SMTP id j76so34838565ioe.0 for ; Wed, 04 Jan 2017 01:11:42 -0800 (PST) In-Reply-To: <1478392821.16546.28.camel@dk-H97M-D3H> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Pandiyan, Dhinakaran" Cc: "Nikula, Jani" , "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org --===============0225253141== Content-Type: multipart/alternative; boundary=001a113ed5404a2bf60545412cc7 --001a113ed5404a2bf60545412cc7 Content-Type: text/plain; charset=UTF-8 Hi On Sun, Nov 6, 2016 at 1:23 AM, Pandiyan, Dhinakaran < dhinakaran.pandiyan@intel.com> wrote: > On Sat, 2016-11-05 at 21:40 +0200, Jani Nikula wrote: > > On Fri, 04 Nov 2016, "Pandiyan, Dhinakaran" < > dhinakaran.pandiyan@intel.com> wrote: > > > On Fri, 2016-11-04 at 17:48 +0200, Jani Nikula wrote: > > >> On Wed, 26 Oct 2016, Dhinakaran Pandiyan < > dhinakaran.pandiyan@intel.com> wrote: > > >> > Enabling DP audio stall fix is necessary to play audio over DP > HBR2. So, > > >> > let's set this bit right before enabling the audio codec. Playing > audio > > >> > without setting this bit results in pipe FIFO underruns. > > >> > > > >> > This workaround is applicable only for audio sample rates up to > 96kHz. For > > >> > frequencies above 96kHz, this is insufficient and cdclk should be > increased > > >> > to at least 432 MHz, just like BDW. Since, the audio driver does not > > >> > support sample rates > 48 kHz, we are safe with this fix for now. > > >> > > >> Do we still need this patch now that these two have been pushed? > > >> > > >> b30ce9e0552a drm/i915/dp: BDW cdclk fix for DP audio > > >> 9c7540241885 drm/i915/dp: Extend BDW DP audio workaround to GEN9 > platforms > > >> > > >> BR, > > >> Jani. > > >> > > >> > > >> > > > > > > No, we are good afaik. This patch would have helped us to make use of a > > > lower cdclk (337.5 MHz), with constraints on audio bit rate. Operating > > > at 432 MHz, like we do now, rules out the need for this patch. > > > > Hmm, what about 5.4 Gbps link with 1 or 2 lanes? > > > > BR, > > Jani. > > > > Good point, I think it will depend on the audio sampling rate. But, I > have to figure out a way to play high sampling rate audio (> 96 KHz) and > test 5.4 Gbps with 1 or 2 lanes. > > The other option is to play safe and apply this patch with even lesser > restrictions, say link rate >= 2.7 Gbps. > > > -DK > as we are currently talking about high samplerates in this context. I wanted to post a perhaps related issue. On my Apollo Lake (J4205) I have two outputs. One DVI and one HDMI 2.0 via internal DP. Via DVI the following works without issues, via DP it fails. As the original commit mentions HBR, I think there is still something missing. We submit TrueHD, DTS-HD via 192 khz and 16 bit format while setting AES0=2 You can easily reproduce with (you obviously need a DTS-HD, TrueHD capable AVR attached to your HDMI 2.0 (DP) out): #TrueHD aplay -D 'hdmi:CARD=PCH,DEV=0,AES0=2' -c8 -fs16_le -r192000 testi.truehd.anssi1.ff.60s.spdif #DTS-HD aplay -D 'hdmi:CARD=PCH,DEV=0,AES0=2' -c8 -fs16_le -r192000 testi.dtshd.anssi1.ma-71-24.spdif Samples: http://www.avenard.org/files/media/mediatest/audiotest/HDAUDIO/Passthrough/ For the old HDMI 1.x chips it was fixed via: https://bugs.freedesktop.org/show_bug.cgi?id=49055 Is this also planned for DP within that patch series? Best regards Peter > > > > > > > -DK > > > > > >> > > > >> > v2: Inlined the code change within hsw_audio_codec_enable() (Jani) > > >> > Fixed the port clock typo > > >> > Added TODO comment > > >> > Signed-off-by: Dhinakaran Pandiyan > > >> > --- > > >> > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ > > >> > drivers/gpu/drm/i915/intel_audio.c | 30 > +++++++++++++++++++++++++++++- > > >> > 2 files changed, 34 insertions(+), 1 deletion(-) > > >> > > > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > > >> > index 00efaa1..76dac48 100644 > > >> > --- a/drivers/gpu/drm/i915/i915_reg.h > > >> > +++ b/drivers/gpu/drm/i915/i915_reg.h > > >> > @@ -6236,6 +6236,11 @@ enum { > > >> > #define SLICE_ECO_CHICKEN0 _MMIO(0x7308) > > >> > #define PIXEL_MASK_CAMMING_DISABLE (1 << 14) > > >> > > > >> > +#define _CHICKEN_TRANS_A 0x420C0 > > >> > +#define _CHICKEN_TRANS_B 0x420C4 > > >> > +#define CHICKEN_TRANS(tran) _MMIO_TRANS(tran, _CHICKEN_TRANS_A, > _CHICKEN_TRANS_B) > > >> > +#define SPARE_13 (1<<13) > > >> > + > > >> > /* WaCatErrorRejectionIssue */ > > >> > #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) > > >> > #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) > > >> > diff --git a/drivers/gpu/drm/i915/intel_audio.c > b/drivers/gpu/drm/i915/intel_audio.c > > >> > index 7093cfb..894f11e 100644 > > >> > --- a/drivers/gpu/drm/i915/intel_audio.c > > >> > +++ b/drivers/gpu/drm/i915/intel_audio.c > > >> > @@ -283,6 +283,8 @@ static void hsw_audio_codec_disable(struct > intel_encoder *encoder) > > >> > { > > >> > struct drm_i915_private *dev_priv = > to_i915(encoder->base.dev); > > >> > struct intel_crtc *intel_crtc = > to_intel_crtc(encoder->base.crtc); > > >> > + struct intel_crtc_state *crtc_config = intel_crtc->config; > > >> > + enum transcoder cpu_transcoder = > crtc_config->cpu_transcoder; > > >> > enum pipe pipe = intel_crtc->pipe; > > >> > uint32_t tmp; > > >> > > > >> > @@ -290,13 +292,21 @@ static void hsw_audio_codec_disable(struct > intel_encoder *encoder) > > >> > > > >> > mutex_lock(&dev_priv->av_mutex); > > >> > > > >> > + /*Disable DP audio stall fix for HBR2*/ > > >> > + if (IS_GEN9(dev_priv) && intel_crtc_has_dp_encoder(crtc_config) > && > > >> > + crtc_config->port_clock >= 540000) { > > >> > + tmp = I915_READ(CHICKEN_TRANS(cpu_transcoder)); > > >> > + tmp &= ~SPARE_13; > > >> > + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), tmp); > > >> > + } > > >> > + > > >> > /* Disable timestamps */ > > >> > tmp = I915_READ(HSW_AUD_CFG(pipe)); > > >> > tmp &= ~AUD_CONFIG_N_VALUE_INDEX; > > >> > tmp |= AUD_CONFIG_N_PROG_ENABLE; > > >> > tmp &= ~AUD_CONFIG_UPPER_N_MASK; > > >> > tmp &= ~AUD_CONFIG_LOWER_N_MASK; > > >> > - if (intel_crtc_has_dp_encoder(intel_crtc->config)) > > >> > + if (intel_crtc_has_dp_encoder(crtc_config)) > > >> > tmp |= AUD_CONFIG_N_VALUE_INDEX; > > >> > I915_WRITE(HSW_AUD_CFG(pipe), tmp); > > >> > > > >> > @@ -315,6 +325,8 @@ static void hsw_audio_codec_enable(struct > drm_connector *connector, > > >> > { > > >> > struct drm_i915_private *dev_priv = > to_i915(connector->dev); > > >> > struct intel_crtc *intel_crtc = > to_intel_crtc(intel_encoder->base.crtc); > > >> > + struct intel_crtc_state *crtc_config = intel_crtc->config; > > >> > + enum transcoder cpu_transcoder = > crtc_config->cpu_transcoder; > > >> > enum pipe pipe = intel_crtc->pipe; > > >> > enum port port = intel_encoder->port; > > >> > const uint8_t *eld = connector->eld; > > >> > @@ -326,6 +338,22 @@ static void hsw_audio_codec_enable(struct > drm_connector *connector, > > >> > > > >> > mutex_lock(&dev_priv->av_mutex); > > >> > > > >> > + /* Enable DP audio stall fix for HBR2 > > >> > + * > > >> > + * TODO: This workaround is applicable only for audio > sample rates up > > >> > + * to 96kHz. For frequencies above 96kHz, this is > insufficient and > > >> > + * cdclk should be increased to at least 432 MHz, just > like BDW. Since, > > >> > + * the audio driver does not support sample rates > 48 > kHz, we are safe > > >> > + * with this fix for now. > > >> > + */ > > >> > + > > >> > + if (IS_GEN9(dev_priv) && intel_crtc_has_dp_encoder(crtc_config) > && > > >> > + crtc_config->port_clock >= 540000) { > > >> > + tmp = I915_READ(CHICKEN_TRANS(cpu_transcoder)); > > >> > + tmp |= SPARE_13; > > >> > + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), tmp); > > >> > + } > > >> > + > > >> > /* Enable audio presence detect, invalidate ELD */ > > >> > tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); > > >> > tmp |= AUDIO_OUTPUT_ENABLE(pipe); > > >> > > > > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > --001a113ed5404a2bf60545412cc7 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Hi

On Sun, Nov 6, 2016 at 1:23 AM, Pandiyan, Dhinakaran &l= t;dhinak= aran.pandiyan@intel.com> wrote:
On Sat, 2016-11-05 at 21:40 = +0200, Jani Nikula wrote:
> On Fri, 04 Nov 2016, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com= > wrote:
> > On Fri, 2016-11-04 at 17:48 +0200, Jani Nikula wrote:
> >> On Wed, 26 Oct 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>= wrote:
> >> > Enabling DP audio stall fix is necessary to play audio o= ver DP HBR2. So,
> >> > let's set this bit right before enabling the audio c= odec. Playing audio
> >> > without setting this bit results in pipe FIFO underruns.=
> >> >
> >> > This workaround is applicable only for audio sample rate= s up to 96kHz. For
> >> > frequencies above 96kHz, this is insufficient and cdclk = should be increased
> >> > to at least 432 MHz, just like BDW. Since, the audio dri= ver does not
> >> > support sample rates > 48 kHz, we are safe with this = fix for now.
> >>
> >> Do we still need this patch now that these two have been push= ed?
> >>
> >> b30ce9e0552a drm/i915/dp: BDW cdclk fix for DP audio
> >> 9c7540241885 drm/i915/dp: Extend BDW DP audio workaround to G= EN9 platforms
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >>
> >
> > No, we are good afaik. This patch would have helped us to make us= e of a
> > lower cdclk (337.5 MHz), with constraints on audio bit rate. Oper= ating
> > at 432 MHz, like we do now, rules out the need for this patch. >
> Hmm, what about 5.4 Gbps link with 1 or 2 lanes?
>
> BR,
> Jani.
>

Good point, I think it will depend on the audio sampling rate. But, = I
have to figure out a way to play high sampling rate audio (> 96 KHz) and=
test 5.4 Gbps with 1 or 2 lanes.

The other option is to play safe and apply this patch with even lesser
restrictions, say link rate >=3D 2.7 Gbps.


-DK

as we are currently talking about h= igh samplerates in this context. I wanted to post a perhaps related issue. = On my Apollo Lake (J4205) I have two outputs. One DVI and one HDMI 2.0 via = internal DP. Via DVI the following works without issues, via DP it fails. A= s the original commit mentions HBR, I think there is still something missin= g. We submit TrueHD, DTS-HD via 192 khz and 16 bit format while setting AES= 0=3D2

You can easily reproduce with (you obviously= need a DTS-HD, TrueHD capable AVR attached to your HDMI 2.0 (DP) out):

#TrueHD
aplay -D 'hdmi:CARD=3DPCH,DEV=3D0,AES0=3D2&= #39; -c8 -fs16_le -r192000 testi.truehd.anssi1.ff.60s.spdif
#DTS-HD
a= play -D 'hdmi:CARD=3DPCH,DEV=3D0,AES0=3D2' -c8 -fs16_le -r192000 te= sti.dtshd.anssi1.ma-71-24.spdif
For the old HDMI 1.x chips it was fixed via: https://bugs.freedeskto= p.org/show_bug.cgi?id=3D49055

Is this also pla= nned for DP within that patch series?

Best regards=
Peter=C2=A0

> >
> > -DK
> >
> >> >
> >> > v2: Inlined the code change within hsw_audio_codec_enabl= e() (Jani)
> >> >=C2=A0 =C2=A0 =C2=A0Fixed the port clock typo
> >> >=C2=A0 =C2=A0 =C2=A0Added TODO comment
> >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com><= br> > >> > ---
> >> >=C2=A0 drivers/gpu/drm/i915/i915_reg.h=C2=A0 =C2=A0 = |=C2=A0 5 +++++
> >> >=C2=A0 drivers/gpu/drm/i915/intel_audio.c | 30 +++++= ++++++++++++++++++++++++-
> >> >=C2=A0 2 files changed, 34 insertions(+), 1 deletion(-) > >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/driv= ers/gpu/drm/i915/i915_reg.h
> >> > index 00efaa1..76dac48 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -6236,6 +6236,11 @@ enum {
> >> >=C2=A0 #define SLICE_ECO_CHICKEN0=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 _MMIO(0x7308)
> >> >=C2=A0 #define=C2=A0 =C2=A0PIXEL_MASK_CAMMING_DISABLE=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 14)
> >> >
> >> > +#define _CHICKEN_TRANS_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x4= 20C0
> >> > +#define _CHICKEN_TRANS_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x4= 20C4
> >> > +#define CHICKEN_TRANS(tran) _MMIO_TRANS(tran, _CHICKEN_= TRANS_A, _CHICKEN_TRANS_B)
> >> > +#define SPARE_13=C2=A0 =C2=A0 =C2=A0 =C2=A0 (1<<1= 3)
> >> > +
> >> >=C2=A0 /* WaCatErrorRejectionIssue */
> >> >=C2=A0 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 _MMIO(0x9030)
> >> >=C2=A0 #define=C2=A0 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMO= B=C2=A0 =C2=A0 =C2=A0 =C2=A0(1<<11)
> >> > diff --git a/drivers/gpu/drm/i915/intel_audio.c b/d= rivers/gpu/drm/i915/intel_audio.c
> >> > index 7093cfb..894f11e 100644
> >> > --- a/drivers/gpu/drm/i915/intel_audio.c
> >> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> >> > @@ -283,6 +283,8 @@ static void hsw_audio_codec_disable(= struct intel_encoder *encoder)
> >> >=C2=A0 {
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct drm_i915_privat= e *dev_priv =3D to_i915(encoder->base.dev);
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct intel_crtc *int= el_crtc =3D to_intel_crtc(encoder->base.crtc);
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct intel_crtc_state *cr= tc_config =3D=C2=A0 intel_crtc->config;
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 enum transcoder cpu_transco= der =3D crtc_config->cpu_transcoder;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 enum pipe pipe =3D int= el_crtc->pipe;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t tmp;
> >> >
> >> > @@ -290,13 +292,21 @@ static void hsw_audio_codec_disabl= e(struct intel_encoder *encoder)
> >> >
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mutex_lock(&dev_pr= iv->av_mutex);
> >> >
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*Disable DP audio stall fi= x for HBR2*/
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (IS_GEN9(dev_priv) &= & intel_crtc_has_dp_encoder(crtc_config) &&
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 crtc_config-&= gt;port_clock >=3D 540000) {
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= tmp =3D I915_READ(CHICKEN_TRANS(cpu_transcoder));
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= tmp &=3D ~SPARE_13;
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= I915_WRITE(CHICKEN_TRANS(cpu_transcoder), tmp);
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> >> > +
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Disable timestamps = */
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp =3D I915_READ(HSW_= AUD_CFG(pipe));
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp &=3D ~AUD_CONF= IG_N_VALUE_INDEX;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp |=3D AUD_CONFIG_N_= PROG_ENABLE;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp &=3D ~AUD_CONF= IG_UPPER_N_MASK;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp &=3D ~AUD_CONF= IG_LOWER_N_MASK;
> >> > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (intel_crtc_has_dp_encod= er(intel_crtc->config))
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (intel_crtc_has_dp_encod= er(crtc_config))
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 tmp |=3D AUD_CONFIG_N_VALUE_INDEX;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 I915_WRITE(HSW_AUD_CFG= (pipe), tmp);
> >> >
> >> > @@ -315,6 +325,8 @@ static void hsw_audio_codec_enable(s= truct drm_connector *connector,
> >> >=C2=A0 {
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct drm_i915_privat= e *dev_priv =3D to_i915(connector->dev);
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct intel_crtc *int= el_crtc =3D to_intel_crtc(intel_encoder->base.crtc);
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct intel_crtc_state *cr= tc_config =3D=C2=A0 intel_crtc->config;
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 enum transcoder cpu_transco= der =3D crtc_config->cpu_transcoder;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 enum pipe pipe =3D int= el_crtc->pipe;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 enum port port =3D int= el_encoder->port;
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 const uint8_t *eld =3D= connector->eld;
> >> > @@ -326,6 +338,22 @@ static void hsw_audio_codec_enable(= struct drm_connector *connector,
> >> >
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mutex_lock(&dev_pr= iv->av_mutex);
> >> >
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Enable DP audio stall fi= x for HBR2
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* TODO: This workarou= nd is applicable only for audio sample rates up
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* to 96kHz. For frequ= encies above 96kHz, this is insufficient and
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* cdclk should be inc= reased to at least 432 MHz, just like BDW. Since,
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* the audio driver do= es not support sample rates > 48 kHz, we are safe
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* with this fix for n= ow.
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> >> > +
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (IS_GEN9(dev_priv) &= & intel_crtc_has_dp_encoder(crtc_config) &&
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 crtc_config-&= gt;port_clock >=3D 540000) {
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= tmp =3D I915_READ(CHICKEN_TRANS(cpu_transcoder));
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= tmp |=3D SPARE_13;
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= I915_WRITE(CHICKEN_TRANS(cpu_transcoder), tmp);
> >> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> >> > +
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Enable audio presen= ce detect, invalidate ELD */
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp =3D I915_READ(HSW_= AUD_PIN_ELD_CP_VLD);
> >> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp |=3D AUDIO_OUTPUT_= ENABLE(pipe);
> >>
> >
>

___________= ____________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesk= top.org
https://lists.freedesktop.org/mailman/l= istinfo/intel-gfx

--001a113ed5404a2bf60545412cc7-- --===============0225253141== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============0225253141==--