From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752810AbbCQHlH (ORCPT ); Tue, 17 Mar 2015 03:41:07 -0400 Received: from mail-ig0-f169.google.com ([209.85.213.169]:38067 "EHLO mail-ig0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751744AbbCQHlE convert rfc822-to-8bit (ORCPT ); Tue, 17 Mar 2015 03:41:04 -0400 MIME-Version: 1.0 In-Reply-To: <3714853.Vuc23EfWdL@wuerfel> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> <3714853.Vuc23EfWdL@wuerfel> Date: Tue, 17 Mar 2015 08:41:03 +0100 Message-ID: Subject: Re: [PATCH v2 4/5] PCI: designware: Add disable IO support From: Gabriel Fernandez To: Arnd Bergmann Cc: Kumar Gala , Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , Muralidharan Karicheri , Sachin Kamat , Andrew Lunn , Liviu Dudau , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "kernel@stlinux.com" , linux-pci@vger.kernel.org, Lee Jones Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Arnd, Ok i will try the same way that pci-versatile.c Thanks. Gabriel On 16 March 2015 at 21:00, Arnd Bergmann wrote: > On Monday 16 March 2015 13:00:51 Kumar Gala wrote: >> On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: >> >> > ST sti SoCs PCIe IPs are built around DesignWare IP Core. >> > But in these SoCs PCIe IP doesn't support IO. >> > >> > This patch adds the possibility to disable it through >> > a DT property, by creating an empty IO window and by >> > removing PCI_COMMAND_IO from the setup register. >> > >> > Signed-off-by: Fabrice Gasnier >> > Signed-off-by: Gabriel Fernandez >> > --- >> > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ >> > drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++-- >> > drivers/pci/host/pcie-designware.h | 1 + >> > 3 files changed, 25 insertions(+), 2 deletions(-) >> >> Why not just update the code such that if the ranges doesn’t have an IO >> space rather than introducing a new DT property? > > I suspect we can simplify this now by changing over the designware PCI > code from pci_common_init_dev to calling pci_scan_root_bus() in the > same way that pci-versatile.c does. This would also clean up some > other areas of the driver and let you do proper error handling > in the probe. > > Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriel Fernandez Subject: Re: [PATCH v2 4/5] PCI: designware: Add disable IO support Date: Tue, 17 Mar 2015 08:41:03 +0100 Message-ID: References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> <3714853.Vuc23EfWdL@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <3714853.Vuc23EfWdL@wuerfel> Sender: linux-pci-owner@vger.kernel.org To: Arnd Bergmann Cc: Kumar Gala , Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo List-Id: devicetree@vger.kernel.org Hi Arnd, Ok i will try the same way that pci-versatile.c Thanks. Gabriel On 16 March 2015 at 21:00, Arnd Bergmann wrote: > On Monday 16 March 2015 13:00:51 Kumar Gala wrote: >> On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: >> >> > ST sti SoCs PCIe IPs are built around DesignWare IP Core. >> > But in these SoCs PCIe IP doesn't support IO. >> > >> > This patch adds the possibility to disable it through >> > a DT property, by creating an empty IO window and by >> > removing PCI_COMMAND_IO from the setup register. >> > >> > Signed-off-by: Fabrice Gasnier >> > Signed-off-by: Gabriel Fernandez >> > --- >> > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ >> > drivers/pci/host/pcie-designware.c | 24 ++++++++++= ++++++++++-- >> > drivers/pci/host/pcie-designware.h | 1 + >> > 3 files changed, 25 insertions(+), 2 deletions(-) >> >> Why not just update the code such that if the ranges doesn=E2=80=99t= have an IO >> space rather than introducing a new DT property? > > I suspect we can simplify this now by changing over the designware PC= I > code from pci_common_init_dev to calling pci_scan_root_bus() in the > same way that pci-versatile.c does. This would also clean up some > other areas of the driver and let you do proper error handling > in the probe. > > Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f174.google.com ([209.85.213.174]:36530 "EHLO mail-ig0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752003AbbCQHlE convert rfc822-to-8bit (ORCPT ); Tue, 17 Mar 2015 03:41:04 -0400 Received: by igbue6 with SMTP id ue6so63882912igb.1 for ; Tue, 17 Mar 2015 00:41:04 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <3714853.Vuc23EfWdL@wuerfel> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> <3714853.Vuc23EfWdL@wuerfel> Date: Tue, 17 Mar 2015 08:41:03 +0100 Message-ID: Subject: Re: [PATCH v2 4/5] PCI: designware: Add disable IO support From: Gabriel Fernandez To: Arnd Bergmann Cc: Kumar Gala , Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , Muralidharan Karicheri , Sachin Kamat , Andrew Lunn , Liviu Dudau , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "kernel@stlinux.com" , linux-pci@vger.kernel.org, Lee Jones Content-Type: text/plain; charset=UTF-8 Sender: linux-pci-owner@vger.kernel.org List-ID: Hi Arnd, Ok i will try the same way that pci-versatile.c Thanks. Gabriel On 16 March 2015 at 21:00, Arnd Bergmann wrote: > On Monday 16 March 2015 13:00:51 Kumar Gala wrote: >> On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: >> >> > ST sti SoCs PCIe IPs are built around DesignWare IP Core. >> > But in these SoCs PCIe IP doesn't support IO. >> > >> > This patch adds the possibility to disable it through >> > a DT property, by creating an empty IO window and by >> > removing PCI_COMMAND_IO from the setup register. >> > >> > Signed-off-by: Fabrice Gasnier >> > Signed-off-by: Gabriel Fernandez >> > --- >> > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ >> > drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++-- >> > drivers/pci/host/pcie-designware.h | 1 + >> > 3 files changed, 25 insertions(+), 2 deletions(-) >> >> Why not just update the code such that if the ranges doesn’t have an IO >> space rather than introducing a new DT property? > > I suspect we can simplify this now by changing over the designware PCI > code from pci_common_init_dev to calling pci_scan_root_bus() in the > same way that pci-versatile.c does. This would also clean up some > other areas of the driver and let you do proper error handling > in the probe. > > Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriel.fernandez@linaro.org (Gabriel Fernandez) Date: Tue, 17 Mar 2015 08:41:03 +0100 Subject: [PATCH v2 4/5] PCI: designware: Add disable IO support In-Reply-To: <3714853.Vuc23EfWdL@wuerfel> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-5-git-send-email-gabriel.fernandez@linaro.org> <582D947C-1229-4DD9-BC82-812D1560C49E@codeaurora.org> <3714853.Vuc23EfWdL@wuerfel> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Arnd, Ok i will try the same way that pci-versatile.c Thanks. Gabriel On 16 March 2015 at 21:00, Arnd Bergmann wrote: > On Monday 16 March 2015 13:00:51 Kumar Gala wrote: >> On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ wrote: >> >> > ST sti SoCs PCIe IPs are built around DesignWare IP Core. >> > But in these SoCs PCIe IP doesn't support IO. >> > >> > This patch adds the possibility to disable it through >> > a DT property, by creating an empty IO window and by >> > removing PCI_COMMAND_IO from the setup register. >> > >> > Signed-off-by: Fabrice Gasnier >> > Signed-off-by: Gabriel Fernandez >> > --- >> > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++ >> > drivers/pci/host/pcie-designware.c | 24 ++++++++++++++++++++-- >> > drivers/pci/host/pcie-designware.h | 1 + >> > 3 files changed, 25 insertions(+), 2 deletions(-) >> >> Why not just update the code such that if the ranges doesn?t have an IO >> space rather than introducing a new DT property? > > I suspect we can simplify this now by changing over the designware PCI > code from pci_common_init_dev to calling pci_scan_root_bus() in the > same way that pci-versatile.c does. This would also clean up some > other areas of the driver and let you do proper error handling > in the probe. > > Arnd