From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752880AbbC3M2S (ORCPT ); Mon, 30 Mar 2015 08:28:18 -0400 Received: from mail-oi0-f42.google.com ([209.85.218.42]:35880 "EHLO mail-oi0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752691AbbC3M2N convert rfc822-to-8bit (ORCPT ); Mon, 30 Mar 2015 08:28:13 -0400 MIME-Version: 1.0 In-Reply-To: <20150317114213.GH27081@e106497-lin.cambridge.arm.com> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-3-git-send-email-gabriel.fernandez@linaro.org> <20150317114213.GH27081@e106497-lin.cambridge.arm.com> Date: Mon, 30 Mar 2015 14:28:12 +0200 Message-ID: Subject: Re: [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie From: Gabriel Fernandez To: Liviu Dudau Cc: Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd Bergmann , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , "m-karicheri2@ti.com" , Sachin Kamat , Andrew Lunn , "devicetree@vger.kernel.org" , "kernel@stlinux.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Lee Jones , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Liviu, You're right, i removed configuration space from the ranges. Thanks for reviewing. Gabriel On 17 March 2015 at 12:42, Liviu Dudau wrote: > Hi Gabriel, > > On Mon, Mar 16, 2015 at 02:20:32PM +0000, Gabriel FERNANDEZ wrote: >> sti pcie is built around a Synopsis Designware PCIe IP. >> >> Signed-off-by: Fabrice Gasnier >> Signed-off-by: Gabriel Fernandez >> --- >> Documentation/devicetree/bindings/pci/st-pcie.txt | 54 +++++++++++++++++++++++ >> 1 file changed, 54 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt >> >> diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt >> new file mode 100644 >> index 0000000..94aae2d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt >> @@ -0,0 +1,54 @@ >> +STMicroelectronics STi PCIe controller >> + >> +This PCIe host controller is based on the Synopsis Designware PCIe IP >> +and thus inherits all the common properties defined in designware-pcie.txt. >> + >> +Required properties: >> + - compatible: "st,stih407-pcie" >> + - reg: base address and length of the pcie controller, mem-window address >> + and length available to the controller. >> + - interrupts: A list of interrupt outputs of the controller. Must contain an >> + entry for each entry in the interrupt-names property. >> + - interrupt-names: Should be "msi". STi interrupt that is asserted when an >> + MSI is received. >> + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg >> + offset for IP configuration. >> + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. >> + Associated names must be "powerdown" and "softreset". >> + - phys, phy-names: the phandle for the PHY device. >> + Associated name must be "pcie" >> + >> +Optional properties: >> + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. >> + >> +Example: >> + >> +pcie0: pcie@9b00000 { >> + compatible = "st,stih407-pcie", "snps,dw-pcie"; >> + device_type = "pci"; >> + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ >> + <0x2fff0000 0x00010000>, /* configuration space */ >> + <0x40000000 0x80000000>; /* lmi mem window */ >> + reg-names = "dbi", "config", "mem-window"; >> + st,syscfg = <&syscfg_core 0xd8 0xe0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x00000800 0 0x2fff0000 0x2fff0000 0 0x00010000 /* configuration space */ > > Unless you are trying to support some legacy code please remove the configuration space from the ranges. > There is no resource type associated with config space and the generic parser will give you back an > invalid resource type. The other reason for that is that if you really claim to be ECAM compliant by > adding the config space here you need way more than 64K of space. > > Best regards, > Liviu > >> + 0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ >> + num-lanes = <1>; >> + interrupts = ; >> + interrupt-names = "msi"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ >> + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ >> + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ >> + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ >> + >> + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, >> + <&softreset STIH407_PCIE0_SOFTRESET>; >> + reset-names = "powerdown", >> + "softreset"; >> + phys = <&phy_port0 PHY_TYPE_PCIE>; >> + phy-names = "pcie"; >> +}; >> -- >> 1.9.1 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > > -- > ==================== > | I would like to | > | fix the world, | > | but they're not | > | giving me the | > \ source code! / > --------------- > ¯\_(ツ)_/¯ > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriel Fernandez Subject: Re: [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie Date: Mon, 30 Mar 2015 14:28:12 +0200 Message-ID: References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-3-git-send-email-gabriel.fernandez@linaro.org> <20150317114213.GH27081@e106497-lin.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20150317114213.GH27081-2JSQmVVBSi7ZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Liviu Dudau Cc: Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd List-Id: devicetree@vger.kernel.org Hi Liviu, You're right, i removed configuration space from the ranges. Thanks for reviewing. Gabriel On 17 March 2015 at 12:42, Liviu Dudau wrote: > Hi Gabriel, > > On Mon, Mar 16, 2015 at 02:20:32PM +0000, Gabriel FERNANDEZ wrote: >> sti pcie is built around a Synopsis Designware PCIe IP. >> >> Signed-off-by: Fabrice Gasnier >> Signed-off-by: Gabriel Fernandez >> --- >> Documentation/devicetree/bindings/pci/st-pcie.txt | 54 ++++++++++++= +++++++++++ >> 1 file changed, 54 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.tx= t >> >> diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Doc= umentation/devicetree/bindings/pci/st-pcie.txt >> new file mode 100644 >> index 0000000..94aae2d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt >> @@ -0,0 +1,54 @@ >> +STMicroelectronics STi PCIe controller >> + >> +This PCIe host controller is based on the Synopsis Designware PCIe = IP >> +and thus inherits all the common properties defined in designware-p= cie.txt. >> + >> +Required properties: >> + - compatible: "st,stih407-pcie" >> + - reg: base address and length of the pcie controller, mem-window = address >> + and length available to the controller. >> + - interrupts: A list of interrupt outputs of the controller. Must = contain an >> + entry for each entry in the interrupt-names property. >> + - interrupt-names: Should be "msi". STi interrupt that is asserted= when an >> + MSI is received. >> + - st,syscfg : should be a phandle of the syscfg node. Also contain= s syscfg >> + offset for IP configuration. >> + - resets, reset-names: the power-down and soft-reset lines of PCIe= IP. >> + Associated names must be "powerdown" and "softreset". >> + - phys, phy-names: the phandle for the PHY device. >> + Associated name must be "pcie" >> + >> +Optional properties: >> + - reset-gpio: a GPIO spec to define which pin is connected to the = bus reset. >> + >> +Example: >> + >> +pcie0: pcie@9b00000 { >> + compatible =3D "st,stih407-pcie", "snps,dw-pcie"; >> + device_type =3D "pci"; >> + reg =3D <0x09b00000 0x4000>, /* dbi cntrl registers */ >> + <0x2fff0000 0x00010000>, /* configuration space */ >> + <0x40000000 0x80000000>; /* lmi mem window */ >> + reg-names =3D "dbi", "config", "mem-window"; >> + st,syscfg =3D <&syscfg_core 0xd8 0xe0>; >> + #address-cells =3D <3>; >> + #size-cells =3D <2>; >> + ranges =3D <0x00000800 0 0x2fff0000 0x2fff0000 0 0x00010000 = /* configuration space */ > > Unless you are trying to support some legacy code please remove the c= onfiguration space from the ranges. > There is no resource type associated with config space and the generi= c parser will give you back an > invalid resource type. The other reason for that is that if you reall= y claim to be ECAM compliant by > adding the config space here you need way more than 64K of space. > > Best regards, > Liviu > >> + 0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /*= non-prefetchable memory */ >> + num-lanes =3D <1>; >> + interrupts =3D ; >> + interrupt-names =3D "msi"; >> + #interrupt-cells =3D <1>; >> + interrupt-map-mask =3D <0 0 0 7>; >> + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HI= GH>, /* INT A */ >> + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH= >, /* INT B */ >> + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH= >, /* INT C */ >> + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH= >; /* INT D */ >> + >> + resets =3D <&powerdown STIH407_PCIE0_POWERDOWN>, >> + <&softreset STIH407_PCIE0_SOFTRESET>; >> + reset-names =3D "powerdown", >> + "softreset"; >> + phys =3D <&phy_port0 PHY_TYPE_PCIE>; >> + phy-names =3D "pcie"; >> +}; >> -- >> 1.9.1 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > > -- > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > | I would like to | > | fix the world, | > | but they're not | > | giving me the | > \ source code! / > --------------- > =C2=AF\_(=E3=83=84)_/=C2=AF > -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-f48.google.com ([209.85.218.48]:33576 "EHLO mail-oi0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752437AbbC3M2N convert rfc822-to-8bit (ORCPT ); Mon, 30 Mar 2015 08:28:13 -0400 Received: by oifl3 with SMTP id l3so126894037oif.0 for ; Mon, 30 Mar 2015 05:28:12 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20150317114213.GH27081@e106497-lin.cambridge.arm.com> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-3-git-send-email-gabriel.fernandez@linaro.org> <20150317114213.GH27081@e106497-lin.cambridge.arm.com> Date: Mon, 30 Mar 2015 14:28:12 +0200 Message-ID: Subject: Re: [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie From: Gabriel Fernandez To: Liviu Dudau Cc: Gabriel FERNANDEZ , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Mohit Kumar , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , "David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd Bergmann , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , "m-karicheri2@ti.com" , Sachin Kamat , Andrew Lunn , "devicetree@vger.kernel.org" , "kernel@stlinux.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Lee Jones , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-pci-owner@vger.kernel.org List-ID: Hi Liviu, You're right, i removed configuration space from the ranges. Thanks for reviewing. Gabriel On 17 March 2015 at 12:42, Liviu Dudau wrote: > Hi Gabriel, > > On Mon, Mar 16, 2015 at 02:20:32PM +0000, Gabriel FERNANDEZ wrote: >> sti pcie is built around a Synopsis Designware PCIe IP. >> >> Signed-off-by: Fabrice Gasnier >> Signed-off-by: Gabriel Fernandez >> --- >> Documentation/devicetree/bindings/pci/st-pcie.txt | 54 +++++++++++++++++++++++ >> 1 file changed, 54 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt >> >> diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt >> new file mode 100644 >> index 0000000..94aae2d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt >> @@ -0,0 +1,54 @@ >> +STMicroelectronics STi PCIe controller >> + >> +This PCIe host controller is based on the Synopsis Designware PCIe IP >> +and thus inherits all the common properties defined in designware-pcie.txt. >> + >> +Required properties: >> + - compatible: "st,stih407-pcie" >> + - reg: base address and length of the pcie controller, mem-window address >> + and length available to the controller. >> + - interrupts: A list of interrupt outputs of the controller. Must contain an >> + entry for each entry in the interrupt-names property. >> + - interrupt-names: Should be "msi". STi interrupt that is asserted when an >> + MSI is received. >> + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg >> + offset for IP configuration. >> + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. >> + Associated names must be "powerdown" and "softreset". >> + - phys, phy-names: the phandle for the PHY device. >> + Associated name must be "pcie" >> + >> +Optional properties: >> + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. >> + >> +Example: >> + >> +pcie0: pcie@9b00000 { >> + compatible = "st,stih407-pcie", "snps,dw-pcie"; >> + device_type = "pci"; >> + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ >> + <0x2fff0000 0x00010000>, /* configuration space */ >> + <0x40000000 0x80000000>; /* lmi mem window */ >> + reg-names = "dbi", "config", "mem-window"; >> + st,syscfg = <&syscfg_core 0xd8 0xe0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x00000800 0 0x2fff0000 0x2fff0000 0 0x00010000 /* configuration space */ > > Unless you are trying to support some legacy code please remove the configuration space from the ranges. > There is no resource type associated with config space and the generic parser will give you back an > invalid resource type. The other reason for that is that if you really claim to be ECAM compliant by > adding the config space here you need way more than 64K of space. > > Best regards, > Liviu > >> + 0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ >> + num-lanes = <1>; >> + interrupts = ; >> + interrupt-names = "msi"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ >> + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ >> + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ >> + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ >> + >> + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, >> + <&softreset STIH407_PCIE0_SOFTRESET>; >> + reset-names = "powerdown", >> + "softreset"; >> + phys = <&phy_port0 PHY_TYPE_PCIE>; >> + phy-names = "pcie"; >> +}; >> -- >> 1.9.1 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > > -- > ==================== > | I would like to | > | fix the world, | > | but they're not | > | giving me the | > \ source code! / > --------------- > ¯\_(ツ)_/¯ > From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriel.fernandez@linaro.org (Gabriel Fernandez) Date: Mon, 30 Mar 2015 14:28:12 +0200 Subject: [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie In-Reply-To: <20150317114213.GH27081@e106497-lin.cambridge.arm.com> References: <1426515635-9466-1-git-send-email-gabriel.fernandez@linaro.org> <1426515635-9466-3-git-send-email-gabriel.fernandez@linaro.org> <20150317114213.GH27081@e106497-lin.cambridge.arm.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Liviu, You're right, i removed configuration space from the ranges. Thanks for reviewing. Gabriel On 17 March 2015 at 12:42, Liviu Dudau wrote: > Hi Gabriel, > > On Mon, Mar 16, 2015 at 02:20:32PM +0000, Gabriel FERNANDEZ wrote: >> sti pcie is built around a Synopsis Designware PCIe IP. >> >> Signed-off-by: Fabrice Gasnier >> Signed-off-by: Gabriel Fernandez >> --- >> Documentation/devicetree/bindings/pci/st-pcie.txt | 54 +++++++++++++++++++++++ >> 1 file changed, 54 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt >> >> diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt >> new file mode 100644 >> index 0000000..94aae2d >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt >> @@ -0,0 +1,54 @@ >> +STMicroelectronics STi PCIe controller >> + >> +This PCIe host controller is based on the Synopsis Designware PCIe IP >> +and thus inherits all the common properties defined in designware-pcie.txt. >> + >> +Required properties: >> + - compatible: "st,stih407-pcie" >> + - reg: base address and length of the pcie controller, mem-window address >> + and length available to the controller. >> + - interrupts: A list of interrupt outputs of the controller. Must contain an >> + entry for each entry in the interrupt-names property. >> + - interrupt-names: Should be "msi". STi interrupt that is asserted when an >> + MSI is received. >> + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg >> + offset for IP configuration. >> + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. >> + Associated names must be "powerdown" and "softreset". >> + - phys, phy-names: the phandle for the PHY device. >> + Associated name must be "pcie" >> + >> +Optional properties: >> + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. >> + >> +Example: >> + >> +pcie0: pcie at 9b00000 { >> + compatible = "st,stih407-pcie", "snps,dw-pcie"; >> + device_type = "pci"; >> + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ >> + <0x2fff0000 0x00010000>, /* configuration space */ >> + <0x40000000 0x80000000>; /* lmi mem window */ >> + reg-names = "dbi", "config", "mem-window"; >> + st,syscfg = <&syscfg_core 0xd8 0xe0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x00000800 0 0x2fff0000 0x2fff0000 0 0x00010000 /* configuration space */ > > Unless you are trying to support some legacy code please remove the configuration space from the ranges. > There is no resource type associated with config space and the generic parser will give you back an > invalid resource type. The other reason for that is that if you really claim to be ECAM compliant by > adding the config space here you need way more than 64K of space. > > Best regards, > Liviu > >> + 0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ >> + num-lanes = <1>; >> + interrupts = ; >> + interrupt-names = "msi"; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 7>; >> + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ >> + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ >> + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ >> + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ >> + >> + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, >> + <&softreset STIH407_PCIE0_SOFTRESET>; >> + reset-names = "powerdown", >> + "softreset"; >> + phys = <&phy_port0 PHY_TYPE_PCIE>; >> + phy-names = "pcie"; >> +}; >> -- >> 1.9.1 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel at lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > > -- > ==================== > | I would like to | > | fix the world, | > | but they're not | > | giving me the | > \ source code! / > --------------- > ?\_(?)_/? >