From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05A6ACCA479 for ; Wed, 22 Jun 2022 23:24:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236540AbiFVXYy (ORCPT ); Wed, 22 Jun 2022 19:24:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358484AbiFVXYx (ORCPT ); Wed, 22 Jun 2022 19:24:53 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CC3942483 for ; Wed, 22 Jun 2022 16:24:52 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id 73-20020a17090a0fcf00b001eaee69f600so890426pjz.1 for ; Wed, 22 Jun 2022 16:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ffIU4qD5x85d6iCQtZLq6rD/cyWC5Mkjs1IUQLDVtmU=; b=SZiUakEUp/fRPbuLjnYU5tXFDGpBGsc7+ny5WQn9Dp9G2PJCoM5kFvXUzrMlLlDF4g 7teOPb905PvRwc/KPgtD+I73FGzZWvYETlPe4rDk5JWVkpGtdBMpI+TBUstC6yyTGvuB BjT8+o4LtU86uDsWnaAAcI7NsVLUt3M0mIIcucXdLLfFNMEVhNmv42ontJ/1GzqiiKJF zTIxkH1mALm3Zy/ScTw+M6+CJNbTaz38LNw3fY1y8oGohl/Pd39TIoSpNnZnB4FOxdbd I5WyQwyN4Q0UshroRddJJocrgQANQeeem6oURxyfwEiVny8ETNlc6ELt/01TvRXEvQvg A+Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ffIU4qD5x85d6iCQtZLq6rD/cyWC5Mkjs1IUQLDVtmU=; b=j8Uukl2crE4CTzaQnD/A3VULPSbmVrTkvvQQPGmU9UpWg3DVxN2aAYy7In7uvfycNH +PgNfBbHAQLDvFygxfmjujxSm49AGIK+irtp0mSLRneiJqTiA9/sFhcjNaoidt95nWSW bz7CdW2ckNQkC5nv0GzC3uAQc9yft7egFNs79QWgPI/I12oF3EkHxEf3vN5nGT5XBBPr VtDKnwoCr4FPwjzEdRJwfmE5KcDTolO38TIo3VBXEug6qyAcxiJITGhhGkxNLVTJeBpN XuPRPYS1m6aRcReHcL4g+1Is8/YWMjDG53h0Vn9zQUUI0vwNttFXoei7LjtVtPxDXoP/ xbfQ== X-Gm-Message-State: AJIora9fuswustyaofZOhfLWuYKXGrwcQkqhF6XUNLse3Jm2QF7eFRmL 2fNUX+Y+0Di9K5LlNe74xjky9XGjyZZXMFVl2W8IPw== X-Google-Smtp-Source: AGRyM1vsB3XLvGTtSV+Qux0xWs8h5I+urr5qnu42v7p9Q5nB2HjwBLTOZs7N+aSdaVrJTMMCj8gnStu06k/O2W5vPpw= X-Received: by 2002:a17:90a:cc7:b0:1ea:3993:78f9 with SMTP id 7-20020a17090a0cc700b001ea399378f9mr812825pjt.179.1655940291540; Wed, 22 Jun 2022 16:24:51 -0700 (PDT) MIME-Version: 1.0 References: <20220621233412.506768-1-robert.foss@linaro.org> <20220621233412.506768-5-robert.foss@linaro.org> In-Reply-To: From: Robert Foss Date: Thu, 23 Jun 2022 01:24:40 +0200 Message-ID: Subject: Re: [PATCH v6 4/6] clk: qcom: add support for SM8350 DISPCC To: Konrad Dybcio Cc: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, 22 Jun 2022 at 12:22, Konrad Dybcio wrote: > > > > On 22.06.2022 01:34, Robert Foss wrote: > > From: Jonathan Marek > > > > Add support to the SM8350 display clock controller by extending the SM8250 > > display clock controller, which is almost identical but has some minor > > differences. > > > > Signed-off-by: Jonathan Marek > > Signed-off-by: Robert Foss > > Reviewed-by: Dmitry Baryshkov > > --- > > > > Changes since v1 > > - Remove comment - Dmitry > > > > Changes since v2 > > - Add my SoB - Bjorn > > - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag > > > > Changes since v3 > > - Add kconfig dependency on SM_GCC_8350 - Konrad > > - Change hex to lowercase - Konrad > > - Split from dispcc-sm8250.c implementation > > - Switch from .fw_name to .index > > > > Changes since v4 > > - Hex to lowercase - Konrad > > - Remove bad match table entries - Konrad > > > > Changes since v5 > > - Reverted split from dispcc-sm8250 > > - Re-added tags from v3 > > > > > > drivers/clk/qcom/Kconfig | 4 +-- > > drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++- > > 2 files changed, 61 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > > index b11235c21952..4c3d1a548b7a 100644 > > --- a/drivers/clk/qcom/Kconfig > > +++ b/drivers/clk/qcom/Kconfig > > @@ -618,11 +618,11 @@ config SM_DISPCC_6125 > > splash screen > > > > config SM_DISPCC_8250 > > - tristate "SM8150 and SM8250 Display Clock Controller" > > + tristate "SM8150/SM8250/SM8350 Display Clock Controller" > > depends on SM_GCC_8150 || SM_GCC_8250 > || SM_GCC_8350 Ack > > > help > > Support for the display clock controller on Qualcomm Technologies, Inc > > - SM8150 and SM8250 devices. > > + SM8150/SM8250/SM8350 devices. > > Say Y if you want to support display devices and functionality such as > > splash screen. > > > > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c > > index db9379634fb2..4e101d584115 100644 > > --- a/drivers/clk/qcom/dispcc-sm8250.c > > +++ b/drivers/clk/qcom/dispcc-sm8250.c > > @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = { > > { 249600000, 2000000000, 0 }, > > }; > > > > +static struct pll_vco lucid_5lpe_vco[] = { > > + { 249600000, 1750000000, 0 }, > > +}; > > + > > static struct alpha_pll_config disp_cc_pll0_config = { > > .l = 0x47, > > .alpha = 0xE000, > > @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { > > { .compatible = "qcom,sc8180x-dispcc" }, > > { .compatible = "qcom,sm8150-dispcc" }, > > { .compatible = "qcom,sm8250-dispcc" }, > > + { .compatible = "qcom,sm8350-dispcc" }, > > { } > > }; > > MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); > > @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > > return PTR_ERR(regmap); > > } > > > > - /* note: trion == lucid, except for the prepare() op */ > > + /* Apply differences for SM8150 and SM8350 */ > I think both comments should stay, as the one you're adding doesn't explain the BUILD_BUG_ON() Ack > > > Konrad > > BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); > > if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || > > of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { > > @@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > > disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; > > disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; > > disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; > > + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { > > + static struct clk_rcg2 * const rcgs[] = { > > + &disp_cc_mdss_byte0_clk_src, > > + &disp_cc_mdss_byte1_clk_src, > > + &disp_cc_mdss_dp_aux1_clk_src, > > + &disp_cc_mdss_dp_aux_clk_src, > > + &disp_cc_mdss_dp_link1_clk_src, > > + &disp_cc_mdss_dp_link_clk_src, > > + &disp_cc_mdss_dp_pixel1_clk_src, > > + &disp_cc_mdss_dp_pixel2_clk_src, > > + &disp_cc_mdss_dp_pixel_clk_src, > > + &disp_cc_mdss_esc0_clk_src, > > + &disp_cc_mdss_mdp_clk_src, > > + &disp_cc_mdss_pclk0_clk_src, > > + &disp_cc_mdss_pclk1_clk_src, > > + &disp_cc_mdss_rot_clk_src, > > + &disp_cc_mdss_vsync_clk_src, > > + }; > > + static struct clk_regmap_div * const divs[] = { > > + &disp_cc_mdss_byte0_div_clk_src, > > + &disp_cc_mdss_byte1_div_clk_src, > > + &disp_cc_mdss_dp_link1_div_clk_src, > > + &disp_cc_mdss_dp_link_div_clk_src, > > + }; > > + unsigned int i; > > + static bool offset_applied; > > + > > + /* only apply the offsets once (in case of deferred probe) */ > > + if (!offset_applied) { > > + for (i = 0; i < ARRAY_SIZE(rcgs); i++) > > + rcgs[i]->cmd_rcgr -= 4; > > + > > + for (i = 0; i < ARRAY_SIZE(divs); i++) { > > + divs[i]->reg -= 4; > > + divs[i]->width = 4; > > + } > > + > > + disp_cc_mdss_ahb_clk.halt_reg -= 4; > > + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; > > + > > + offset_applied = true; > > + } > > + > > + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; > > + > > + disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; > > + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; > > + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > > + disp_cc_pll0.vco_table = lucid_5lpe_vco; > > + disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; > > + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; > > + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > > + disp_cc_pll1.vco_table = lucid_5lpe_vco; > > } > > > > clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);