[PATCH V2 0/2] chrontel-ch7033: Add byteswap order option

[PATCH V2 0/2] chrontel-ch7033: Add byteswap order option

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

This series adds the ability to set the byteswap order in the chrontel
ch7033 driver via an optional devicetree node. This is necessary
because the HDMI DIP of the NTC CHIP requires a byteswap order that
differs from the default value of the driver.

Changes from V1:

 - Updated devicetree documentation to be easier to understand.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>

Chris Morgan (2):
  dt-bindings: Add byteswap order to chrontel ch7033
  drm/bridge: chrontel-ch7033: Add byteswap order setting

 .../bindings/display/bridge/chrontel,ch7033.yaml  | 13 +++++++++++++
 drivers/gpu/drm/bridge/chrontel-ch7033.c          | 15 +++++++++++++--
 2 files changed, 26 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH V2 1/2] dt-bindings: Add byteswap order to chrontel ch7033

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Update dt-binding documentation to add support for setting byteswap of
chrontel ch7033.

New property name of chrontel,byteswap added to set the byteswap order.
This property is optional.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
---
 .../bindings/display/bridge/chrontel,ch7033.yaml    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
index bb6289c7d375..984b90893583 100644
--- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
@@ -14,6 +14,19 @@ properties:
   compatible:
     const: chrontel,ch7033
 
+  chrontel,byteswap:
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum:
+      - 0  # BYTE_SWAP_RGB
+      - 1  # BYTE_SWAP_RBG
+      - 2  # BYTE_SWAP_GRB
+      - 3  # BYTE_SWAP_GBR
+      - 4  # BYTE_SWAP_BRG
+      - 5  # BYTE_SWAP_BGR
+    description: |
+      Set the byteswap value of the bridge. This is optional and if not
+      set value of BYTE_SWAP_BGR is used.
+
   reg:
     maxItems: 1
     description: I2C address of the device
-- 
2.25.1

[PATCH V2 2/2] drm/bridge: chrontel-ch7033: Add byteswap order setting

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

Add the option to set the byteswap order in the devicetree. For the
official HDMI DIP for the NTC CHIP the byteswap order needs to be
RGB, however the driver sets it as BGR. With this patch the driver
will remain at BGR unless manually specified via devicetree.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
---
 drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c
index ba060277c3fd..c5719908ce2d 100644
--- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -68,6 +68,7 @@ enum {
 	BYTE_SWAP_GBR	= 3,
 	BYTE_SWAP_BRG	= 4,
 	BYTE_SWAP_BGR	= 5,
+	BYTE_SWAP_MAX	= 6,
 };
 
 /* Page 0, Register 0x19 */
@@ -355,6 +356,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
 	int hsynclen = mode->hsync_end - mode->hsync_start;
 	int vbporch = mode->vsync_start - mode->vdisplay;
 	int vsynclen = mode->vsync_end - mode->vsync_start;
+	u8 byte_swap;
+	int ret;
 
 	/*
 	 * Page 4
@@ -398,8 +401,16 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
 	regmap_write(priv->regmap, 0x15, vbporch);
 	regmap_write(priv->regmap, 0x16, vsynclen);
 
-	/* Input color swap. */
-	regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
+	/* Input color swap. Byte order is optional and will default to
+	 * BYTE_SWAP_BGR to preserve backwards compatibility with existing
+	 * driver.
+	 */
+	ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
+				  &byte_swap);
+	if (!ret && byte_swap < BYTE_SWAP_MAX)
+		regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
+	else
+		regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
 
 	/* Input clock and sync polarity. */
 	regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
-- 
2.25.1

Re: [PATCH V2 0/2] chrontel-ch7033: Add byteswap order option

[Robert Foss]

On Fri, 2 Sept 2022 at 17:39, Chris Morgan <macroalpha82@gmail.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> This series adds the ability to set the byteswap order in the chrontel
> ch7033 driver via an optional devicetree node. This is necessary
> because the HDMI DIP of the NTC CHIP requires a byteswap order that
> differs from the default value of the driver.
>
> Changes from V1:
>
>  - Updated devicetree documentation to be easier to understand.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>
> Chris Morgan (2):
>   dt-bindings: Add byteswap order to chrontel ch7033
>   drm/bridge: chrontel-ch7033: Add byteswap order setting
>
>  .../bindings/display/bridge/chrontel,ch7033.yaml  | 13 +++++++++++++
>  drivers/gpu/drm/bridge/chrontel-ch7033.c          | 15 +++++++++++++--
>  2 files changed, 26 insertions(+), 2 deletions(-)
>
> --
> 2.25.1
>

Applied to drm-misc-next.

Re: [PATCH V2 2/2] drm/bridge: chrontel-ch7033: Add byteswap order setting

[Laurent Pinchart]

Hi Chris,

Thank you for the patch.

On Fri, Sep 02, 2022 at 10:39:06AM -0500, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Add the option to set the byteswap order in the devicetree. For the
> official HDMI DIP for the NTC CHIP the byteswap order needs to be
> RGB, however the driver sets it as BGR. With this patch the driver
> will remain at BGR unless manually specified via devicetree.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Reviewed-by: Robert Foss <robert.foss@linaro.org>
> ---
>  drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> index ba060277c3fd..c5719908ce2d 100644
> --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
> +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
> @@ -68,6 +68,7 @@ enum {
>  	BYTE_SWAP_GBR	= 3,
>  	BYTE_SWAP_BRG	= 4,
>  	BYTE_SWAP_BGR	= 5,
> +	BYTE_SWAP_MAX	= 6,
>  };
>  
>  /* Page 0, Register 0x19 */
> @@ -355,6 +356,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
>  	int hsynclen = mode->hsync_end - mode->hsync_start;
>  	int vbporch = mode->vsync_start - mode->vdisplay;
>  	int vsynclen = mode->vsync_end - mode->vsync_start;
> +	u8 byte_swap;
> +	int ret;
>  
>  	/*
>  	 * Page 4
> @@ -398,8 +401,16 @@ static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
>  	regmap_write(priv->regmap, 0x15, vbporch);
>  	regmap_write(priv->regmap, 0x16, vsynclen);
>  
> -	/* Input color swap. */
> -	regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
> +	/* Input color swap. Byte order is optional and will default to
> +	 * BYTE_SWAP_BGR to preserve backwards compatibility with existing
> +	 * driver.
> +	 */
> +	ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
> +				  &byte_swap);

That's quite inefficient, please parse the device tree at probe time,
and cache the value.

> +	if (!ret && byte_swap < BYTE_SWAP_MAX)
> +		regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
> +	else
> +		regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
>  
>  	/* Input clock and sync polarity. */
>  	regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);

-- 
Regards,

Laurent Pinchart

Re: [PATCH V2 1/2] dt-bindings: Add byteswap order to chrontel ch7033

[Laurent Pinchart]

Hi Chris,

Thank you for the patch.

On Fri, Sep 02, 2022 at 10:39:05AM -0500, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> Update dt-binding documentation to add support for setting byteswap of
> chrontel ch7033.
> 
> New property name of chrontel,byteswap added to set the byteswap order.
> This property is optional.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Reviewed-by: Robert Foss <robert.foss@linaro.org>
> ---
>  .../bindings/display/bridge/chrontel,ch7033.yaml    | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> index bb6289c7d375..984b90893583 100644
> --- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> @@ -14,6 +14,19 @@ properties:
>    compatible:
>      const: chrontel,ch7033
>  
> +  chrontel,byteswap:
> +    $ref: /schemas/types.yaml#/definitions/uint8
> +    enum:
> +      - 0  # BYTE_SWAP_RGB
> +      - 1  # BYTE_SWAP_RBG
> +      - 2  # BYTE_SWAP_GRB
> +      - 3  # BYTE_SWAP_GBR
> +      - 4  # BYTE_SWAP_BRG
> +      - 5  # BYTE_SWAP_BGR
> +    description: |
> +      Set the byteswap value of the bridge. This is optional and if not
> +      set value of BYTE_SWAP_BGR is used.

I don't think this belongs to the device tree. The source of data
connected to the CH7033 input could use different formats. This
shouldn't be hardcoded, but queried at runtime, using the input and
output media bus formats infrastructure that the DRM bridge framework
includes.

> +
>    reg:
>      maxItems: 1
>      description: I2C address of the device

-- 
Regards,

Laurent Pinchart

Re: [PATCH V2 0/2] chrontel-ch7033: Add byteswap order option

[Laurent Pinchart]

Hi Rob,

On Fri, Sep 02, 2022 at 06:21:50PM +0200, Robert Foss wrote:
> On Fri, 2 Sept 2022 at 17:39, Chris Morgan <macroalpha82@gmail.com> wrote:
> >
> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > This series adds the ability to set the byteswap order in the chrontel
> > ch7033 driver via an optional devicetree node. This is necessary
> > because the HDMI DIP of the NTC CHIP requires a byteswap order that
> > differs from the default value of the driver.
> >
> > Changes from V1:
> >
> >  - Updated devicetree documentation to be easier to understand.
> >
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> >
> > Chris Morgan (2):
> >   dt-bindings: Add byteswap order to chrontel ch7033
> >   drm/bridge: chrontel-ch7033: Add byteswap order setting
> >
> >  .../bindings/display/bridge/chrontel,ch7033.yaml  | 13 +++++++++++++
> >  drivers/gpu/drm/bridge/chrontel-ch7033.c          | 15 +++++++++++++--
> >  2 files changed, 26 insertions(+), 2 deletions(-)
> 
> Applied to drm-misc-next.

I've just reviewed the series, and I don't think this is right. Patch
2/2 has a small issue that could be fixed on top, but more importantly,
I don't think this belongs to DT. See the reply to 1/2.

-- 
Regards,

Laurent Pinchart

Re: [PATCH V2 1/2] dt-bindings: Add byteswap order to chrontel ch7033

[Robert Foss]

Thanks Laurent,

On Sat, 3 Sept 2022 at 02:17, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Hi Chris,
>
> Thank you for the patch.
>
> On Fri, Sep 02, 2022 at 10:39:05AM -0500, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > Update dt-binding documentation to add support for setting byteswap of
> > chrontel ch7033.
> >
> > New property name of chrontel,byteswap added to set the byteswap order.
> > This property is optional.
> >
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > Reviewed-by: Robert Foss <robert.foss@linaro.org>
> > ---
> >  .../bindings/display/bridge/chrontel,ch7033.yaml    | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > index bb6289c7d375..984b90893583 100644
> > --- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > +++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > @@ -14,6 +14,19 @@ properties:
> >    compatible:
> >      const: chrontel,ch7033
> >
> > +  chrontel,byteswap:
> > +    $ref: /schemas/types.yaml#/definitions/uint8
> > +    enum:
> > +      - 0  # BYTE_SWAP_RGB
> > +      - 1  # BYTE_SWAP_RBG
> > +      - 2  # BYTE_SWAP_GRB
> > +      - 3  # BYTE_SWAP_GBR
> > +      - 4  # BYTE_SWAP_BRG
> > +      - 5  # BYTE_SWAP_BGR
> > +    description: |
> > +      Set the byteswap value of the bridge. This is optional and if not
> > +      set value of BYTE_SWAP_BGR is used.
>
> I don't think this belongs to the device tree. The source of data
> connected to the CH7033 input could use different formats. This
> shouldn't be hardcoded, but queried at runtime, using the input and
> output media bus formats infrastructure that the DRM bridge framework
> includes.

Chris, will you have a look at submitting a fix for this during the coming days?

If not, we can revert this series and apply a fixed version later.

>
> > +
> >    reg:
> >      maxItems: 1
> >      description: I2C address of the device
>
> --
> Regards,
>
> Laurent Pinchart

Re: [PATCH V2 1/2] dt-bindings: Add byteswap order to chrontel ch7033

[Chris Morgan]

On Mon, Sep 05, 2022 at 05:20:57PM +0200, Robert Foss wrote:
> Thanks Laurent,
> 
> On Sat, 3 Sept 2022 at 02:17, Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> >
> > Hi Chris,
> >
> > Thank you for the patch.
> >
> > On Fri, Sep 02, 2022 at 10:39:05AM -0500, Chris Morgan wrote:
> > > From: Chris Morgan <macromorgan@hotmail.com>
> > >
> > > Update dt-binding documentation to add support for setting byteswap of
> > > chrontel ch7033.
> > >
> > > New property name of chrontel,byteswap added to set the byteswap order.
> > > This property is optional.
> > >
> > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > > Reviewed-by: Robert Foss <robert.foss@linaro.org>
> > > ---
> > >  .../bindings/display/bridge/chrontel,ch7033.yaml    | 13 +++++++++++++
> > >  1 file changed, 13 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > > index bb6289c7d375..984b90893583 100644
> > > --- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > > +++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > > @@ -14,6 +14,19 @@ properties:
> > >    compatible:
> > >      const: chrontel,ch7033
> > >
> > > +  chrontel,byteswap:
> > > +    $ref: /schemas/types.yaml#/definitions/uint8
> > > +    enum:
> > > +      - 0  # BYTE_SWAP_RGB
> > > +      - 1  # BYTE_SWAP_RBG
> > > +      - 2  # BYTE_SWAP_GRB
> > > +      - 3  # BYTE_SWAP_GBR
> > > +      - 4  # BYTE_SWAP_BRG
> > > +      - 5  # BYTE_SWAP_BGR
> > > +    description: |
> > > +      Set the byteswap value of the bridge. This is optional and if not
> > > +      set value of BYTE_SWAP_BGR is used.
> >
> > I don't think this belongs to the device tree. The source of data
> > connected to the CH7033 input could use different formats. This
> > shouldn't be hardcoded, but queried at runtime, using the input and
> > output media bus formats infrastructure that the DRM bridge framework
> > includes.
> 
> Chris, will you have a look at submitting a fix for this during the coming days?
> 
> If not, we can revert this series and apply a fixed version later.

I'm not sure I understand (or know) what needs to be fixed. Presumably
using something like EDID we can predict what color format we need to
use for the connection between the bridge and the HDMI device, but
wouldn't the color format between the SoC and bridge need to be
constant?

If there's something I'm missing please let me know, I'm relatively
unfamiliar with the display subsystems as a whole. I'll be happy
to make the change once I'm clear what I need to change.

Thank you for your help.

> 
> >
> > > +
> > >    reg:
> > >      maxItems: 1
> > >      description: I2C address of the device
> >
> > --
> > Regards,
> >
> > Laurent Pinchart

Re: [PATCH V2 1/2] dt-bindings: Add byteswap order to chrontel ch7033

[Laurent Pinchart]

Hi Chris,

On Wed, Sep 07, 2022 at 08:29:06AM -0500, Chris Morgan wrote:
> On Mon, Sep 05, 2022 at 05:20:57PM +0200, Robert Foss wrote:
> > On Sat, 3 Sept 2022 at 02:17, Laurent Pinchart wrote:
> > > On Fri, Sep 02, 2022 at 10:39:05AM -0500, Chris Morgan wrote:
> > > > From: Chris Morgan <macromorgan@hotmail.com>
> > > >
> > > > Update dt-binding documentation to add support for setting byteswap of
> > > > chrontel ch7033.
> > > >
> > > > New property name of chrontel,byteswap added to set the byteswap order.
> > > > This property is optional.
> > > >
> > > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > > > Reviewed-by: Robert Foss <robert.foss@linaro.org>
> > > > ---
> > > >  .../bindings/display/bridge/chrontel,ch7033.yaml    | 13 +++++++++++++
> > > >  1 file changed, 13 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > > > index bb6289c7d375..984b90893583 100644
> > > > --- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > > > +++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml
> > > > @@ -14,6 +14,19 @@ properties:
> > > >    compatible:
> > > >      const: chrontel,ch7033
> > > >
> > > > +  chrontel,byteswap:
> > > > +    $ref: /schemas/types.yaml#/definitions/uint8
> > > > +    enum:
> > > > +      - 0  # BYTE_SWAP_RGB
> > > > +      - 1  # BYTE_SWAP_RBG
> > > > +      - 2  # BYTE_SWAP_GRB
> > > > +      - 3  # BYTE_SWAP_GBR
> > > > +      - 4  # BYTE_SWAP_BRG
> > > > +      - 5  # BYTE_SWAP_BGR
> > > > +    description: |
> > > > +      Set the byteswap value of the bridge. This is optional and if not
> > > > +      set value of BYTE_SWAP_BGR is used.
> > >
> > > I don't think this belongs to the device tree. The source of data
> > > connected to the CH7033 input could use different formats. This
> > > shouldn't be hardcoded, but queried at runtime, using the input and
> > > output media bus formats infrastructure that the DRM bridge framework
> > > includes.
> > 
> > Chris, will you have a look at submitting a fix for this during the coming days?
> > 
> > If not, we can revert this series and apply a fixed version later.
> 
> I'm not sure I understand (or know) what needs to be fixed. Presumably
> using something like EDID we can predict what color format we need to
> use for the connection between the bridge and the HDMI device, but
> wouldn't the color format between the SoC and bridge need to be
> constant?

Not necessarily. Some display engines can output different formats. You
should be able to get the selected format at the bridge input from the
drm_bridge_state. Could you please give that a try ?

> If there's something I'm missing please let me know, I'm relatively
> unfamiliar with the display subsystems as a whole. I'll be happy
> to make the change once I'm clear what I need to change.
> 
> Thank you for your help.
> 
> > > > +
> > > >    reg:
> > > >      maxItems: 1
> > > >      description: I2C address of the device

-- 
Regards,

Laurent Pinchart