From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.2 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 621EEC433ED for ; Thu, 29 Apr 2021 01:11:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3EABE61001 for ; Thu, 29 Apr 2021 01:11:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232582AbhD2BMe (ORCPT ); Wed, 28 Apr 2021 21:12:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229624AbhD2BMd (ORCPT ); Wed, 28 Apr 2021 21:12:33 -0400 Received: from mail-yb1-xb32.google.com (mail-yb1-xb32.google.com [IPv6:2607:f8b0:4864:20::b32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B7FBC06138C for ; Wed, 28 Apr 2021 18:11:47 -0700 (PDT) Received: by mail-yb1-xb32.google.com with SMTP id y2so74283194ybq.13 for ; Wed, 28 Apr 2021 18:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=B9WmxfQPgVB/G8qqdqqrH4JxR1XC119NUyqOOtSd7t0=; b=pkiPHPNLc8oPY1Rpg9s6MMH9zsVYb3Pu6hknNjJ97Hfi1mRnSBTaBnKpkK1xFjd1Qc cQcOSKlv6GspGLFBVFS0a2R7wfDy66R5CFpgbbx4KptsbtihfP16CiZn9rhGgXqx5QTW bT7wJSVgy86XNC/E1yQdfItBAZhtztfAwi05/r0kJhF9SMDdROLy1hNoB4qjsCCc7xWl mnFO4W/wNfSaDiAaT4Hzi7/2XKbK/+nwY+9Li/v4xqODqdRq+++/zwuK2aVSJ6jeZ06F W59O7/MT/99ty+gNnLuDf32EQ5etfkSEubBJ3iZEk34moqDnV4u5QwEcMfSvrieB519k avQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=B9WmxfQPgVB/G8qqdqqrH4JxR1XC119NUyqOOtSd7t0=; b=k1Fs+nOdeub89C2ODRoRg16LS/zgJlgmSo6ZvvlUvNk0HbxyNXnoGkA3epOLJGuxGb SAP10NcUkB9rB4q6pY8KkoQKsIB2lTiu1VRWMMaxnHvLRFlBQnJuwyICmX/WvJ0GhfG9 gH/1O//39Z/5BeNlDXzGM2owPQjZEtcZGPn3FQYwckUtUSLoyrgXT7xb2Lkfk1wR9K1t iA3HWiOdRLTex9TbiBotjNIGu7+QMQR03sY8JDwWZNbxMIFLxCSdXW+72EniA7zfzWzO Db96ZT0IPP4pknKZ6m/5fMKSNv0GLdMNVRdMkcF4WEaXJTYGMFa+EvlG1ZEMgApNdk5T X9ww== X-Gm-Message-State: AOAM532qSrngP1RQBrGnl7fWnZ12BceFNkFcjlLDYRqlttdE3g+fRoor wKSFFVxuy1pgUIx4+YdwEhTpq7CuRpHEMCpxoZ24hA== X-Google-Smtp-Source: ABdhPJzGFBnav+DZBGGJcieg9JxgTULrcj3YfzoYD2uRXeNcTYI7rbQImezTdi5sUdA9XukgcMPYmupPisXhoBxFVf8= X-Received: by 2002:a25:58d5:: with SMTP id m204mr47013043ybb.32.1619658706418; Wed, 28 Apr 2021 18:11:46 -0700 (PDT) MIME-Version: 1.0 References: <20210428222953.235280-1-sebastian.reichel@collabora.com> <20210428222953.235280-2-sebastian.reichel@collabora.com> In-Reply-To: <20210428222953.235280-2-sebastian.reichel@collabora.com> From: Saravana Kannan Date: Wed, 28 Apr 2021 18:11:10 -0700 Message-ID: Subject: Re: [PATCHv2 1/5] rtc: m41t80: add support for fixed clock To: Sebastian Reichel Cc: Philipp Zabel , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Rob Herring , Alexandre Belloni , Alessandro Zummo , David Airlie , Daniel Vetter , Miquel Raynal , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , dri-devel , linux-arm-kernel , LKML , linux-rtc@vger.kernel.org, linux-mtd@lists.infradead.org, Collabora Kernel ML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 28, 2021 at 3:29 PM Sebastian Reichel wrote: > > Congatec's QMX6 system on module (SoM) uses a m41t62 as RTC. The > modules SQW clock output defaults to 32768 Hz. This behaviour is > used to provide the i.MX6 CKIL clock. Once the RTC driver is probed, > the clock is disabled and all i.MX6 functionality depending on > the 32 KHz clock has undefined behaviour. For example when using > the hardware watchdog the system will likely do arbitrary reboots. > > Referencing the m41t62 directly results in a deadlock. The kernel > will see, that i.MX6 system clock needs the RTC clock and do probe > deferral. But the i.MX6 I2C module never becomes usable without the > i.MX6 CKIL clock and thus the RTC's clock will not be probed. So > from the kernel's perspective this is a chicken-and-egg problem. > > Technically everything is fine by not touching anything, since > the RTC clock correctly enables the clock on reset (i.e. on > battery backup power loss) and also the bootloader enables it > in case an something (e.g. an unpatched kernel) disabled this > incorrectly. > > A workaround for this issue is describing the square wave pin > as fixed-clock, which is registered early and basically how > this pin is used on the i.MX6. > > Suggested-by: Saravana Kannan > Signed-off-by: Sebastian Reichel > --- > Documentation/devicetree/bindings/rtc/rtc-m41t80.txt | 9 +++++++++ > drivers/rtc/rtc-m41t80.c | 12 ++++++++++++ > 2 files changed, 21 insertions(+) > > diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > index c746cb221210..cdd196b1e9bd 100644 > --- a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > +++ b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > @@ -21,10 +21,19 @@ Optional properties: > clock name > - wakeup-source: Enables wake up of host system on alarm > > +Optional child node: > +- clock: Provide this if the square wave pin is used as boot-enabled fixed clock. > + > Example: > rtc@68 { > compatible = "st,m41t80"; > reg = <0x68>; > interrupt-parent = <&UIC0>; > interrupts = <0x9 0x8>; > + > + clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + }; > }; > diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c > index 89128fc29ccc..b3ece42b6f90 100644 > --- a/drivers/rtc/rtc-m41t80.c > +++ b/drivers/rtc/rtc-m41t80.c > @@ -544,10 +544,22 @@ static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80) > { > struct i2c_client *client = m41t80->client; > struct device_node *node = client->dev.of_node; > + struct device_node *fixed_clock; > struct clk *clk; > struct clk_init_data init; > int ret; > > + fixed_clock = of_get_child_by_name(node, "clock"); > + if (fixed_clock) { > + /* > + * skip registering square wave clock when a fixed > + * clock has been registered. The fixed clock is > + * registered automatically when being referenced. > + */ > + of_node_put(fixed_clock); > + return 0; > + } > + > /* First disable the clock */ > ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); > if (ret < 0) Reviewed-by: Saravana Kannan -Saravana From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6957EC433ED for ; Thu, 29 Apr 2021 01:13:18 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D1E866143B for ; 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bh=B9WmxfQPgVB/G8qqdqqrH4JxR1XC119NUyqOOtSd7t0=; b=jCnUFyTMWM8Sds/cPAZhHb+9BIBLu89Za33iGvkumfD8zg1FCo+yjKLabEF10teGvq 0rQVbw7qi3rYNzetHs8dhrugexQSLedynLk4jpbFbJ4AQErC/i/IHm3VtG2bMVqTf/hM T2zlKsg7YAlzIG4oZjlxU88aMVngdU2HwNWWIjCpWYVq5wCxXw2Ggg0Bl3D3H75pQd41 1XK7gvXuieR6SZL+ylkYtoLIc6sNoY+oOI49M8ZM0lBHat0vZSiB7FkcT6Zb/iAIu1mZ 6ud2lzIYgpJW3NLrES3xQRBDAWw1qd3+a8Ei/9CZirwKjUED6ur1DtGxGpN5JPsx4uAe vYGw== X-Gm-Message-State: AOAM531Puqap0weSOB5HQTOGJtYhVDE4C60y9yO53Mvp69qskrDoIuAh xb4jtyCXzGu+A4zESlkbEjJUXsOfTdN2VfvnLOBQmg== X-Google-Smtp-Source: ABdhPJzGFBnav+DZBGGJcieg9JxgTULrcj3YfzoYD2uRXeNcTYI7rbQImezTdi5sUdA9XukgcMPYmupPisXhoBxFVf8= X-Received: by 2002:a25:58d5:: with SMTP id m204mr47013043ybb.32.1619658706418; Wed, 28 Apr 2021 18:11:46 -0700 (PDT) MIME-Version: 1.0 References: <20210428222953.235280-1-sebastian.reichel@collabora.com> <20210428222953.235280-2-sebastian.reichel@collabora.com> In-Reply-To: <20210428222953.235280-2-sebastian.reichel@collabora.com> From: Saravana Kannan Date: Wed, 28 Apr 2021 18:11:10 -0700 Message-ID: Subject: Re: [PATCHv2 1/5] rtc: m41t80: add support for fixed clock To: Sebastian Reichel Cc: Philipp Zabel , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Rob Herring , Alexandre Belloni , Alessandro Zummo , David Airlie , Daniel Vetter , Miquel Raynal , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , dri-devel , linux-arm-kernel , LKML , linux-rtc@vger.kernel.org, linux-mtd@lists.infradead.org, Collabora Kernel ML X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210428_181148_978154_C8FADDB2 X-CRM114-Status: GOOD ( 27.66 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Wed, Apr 28, 2021 at 3:29 PM Sebastian Reichel wrote: > > Congatec's QMX6 system on module (SoM) uses a m41t62 as RTC. The > modules SQW clock output defaults to 32768 Hz. This behaviour is > used to provide the i.MX6 CKIL clock. Once the RTC driver is probed, > the clock is disabled and all i.MX6 functionality depending on > the 32 KHz clock has undefined behaviour. For example when using > the hardware watchdog the system will likely do arbitrary reboots. > > Referencing the m41t62 directly results in a deadlock. The kernel > will see, that i.MX6 system clock needs the RTC clock and do probe > deferral. But the i.MX6 I2C module never becomes usable without the > i.MX6 CKIL clock and thus the RTC's clock will not be probed. So > from the kernel's perspective this is a chicken-and-egg problem. > > Technically everything is fine by not touching anything, since > the RTC clock correctly enables the clock on reset (i.e. on > battery backup power loss) and also the bootloader enables it > in case an something (e.g. an unpatched kernel) disabled this > incorrectly. > > A workaround for this issue is describing the square wave pin > as fixed-clock, which is registered early and basically how > this pin is used on the i.MX6. > > Suggested-by: Saravana Kannan > Signed-off-by: Sebastian Reichel > --- > Documentation/devicetree/bindings/rtc/rtc-m41t80.txt | 9 +++++++++ > drivers/rtc/rtc-m41t80.c | 12 ++++++++++++ > 2 files changed, 21 insertions(+) > > diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > index c746cb221210..cdd196b1e9bd 100644 > --- a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > +++ b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > @@ -21,10 +21,19 @@ Optional properties: > clock name > - wakeup-source: Enables wake up of host system on alarm > > +Optional child node: > +- clock: Provide this if the square wave pin is used as boot-enabled fixed clock. > + > Example: > rtc@68 { > compatible = "st,m41t80"; > reg = <0x68>; > interrupt-parent = <&UIC0>; > interrupts = <0x9 0x8>; > + > + clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + }; > }; > diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c > index 89128fc29ccc..b3ece42b6f90 100644 > --- a/drivers/rtc/rtc-m41t80.c > +++ b/drivers/rtc/rtc-m41t80.c > @@ -544,10 +544,22 @@ static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80) > { > struct i2c_client *client = m41t80->client; > struct device_node *node = client->dev.of_node; > + struct device_node *fixed_clock; > struct clk *clk; > struct clk_init_data init; > int ret; > > + fixed_clock = of_get_child_by_name(node, "clock"); > + if (fixed_clock) { > + /* > + * skip registering square wave clock when a fixed > + * clock has been registered. The fixed clock is > + * registered automatically when being referenced. > + */ > + of_node_put(fixed_clock); > + return 0; > + } > + > /* First disable the clock */ > ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); > if (ret < 0) Reviewed-by: Saravana Kannan -Saravana ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81E86C433B4 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=B9WmxfQPgVB/G8qqdqqrH4JxR1XC119NUyqOOtSd7t0=; b=m1VDu39qDqBDhHhv3SJDHda0uwOw0AtkgHmF8QnAn4NAQ3+bRyxZ59qWR3w3nRCAy+ T998XU0kneRWNIV15qC8lcWWP69Na+TNdrJGIZ49n8DyAyTJCm0fvHOn0f+0LTeWt1qk PtUo51TaVPTxuARBb1esQ3wfhlmnI7XE4bXdB1+wwKap0Qx/zPXqGhNjZ0N8OsGPhA8T SoBRyXohlToHuE0uiedAZQlOQuNKszSRlzrMBWPhJQ59p9lFl1TtDjN413O9rUQ3HKog ibSJYxzLgUkmsqN5fpc/j68kBxW59WhPYL5/iSa1Wyceflyi2AHtGmpLbNi55TdWKdPV QpmQ== X-Gm-Message-State: AOAM530m54ajyy6XqPqr9vFulwv9RnrQUw1lW2xOZzBv8WXPj6BdTnhz y4BL5O/fDCsgNWRY7nw+TnVrIsVcTe/Cf5bewrn6wQ== X-Google-Smtp-Source: ABdhPJzGFBnav+DZBGGJcieg9JxgTULrcj3YfzoYD2uRXeNcTYI7rbQImezTdi5sUdA9XukgcMPYmupPisXhoBxFVf8= X-Received: by 2002:a25:58d5:: with SMTP id m204mr47013043ybb.32.1619658706418; Wed, 28 Apr 2021 18:11:46 -0700 (PDT) MIME-Version: 1.0 References: <20210428222953.235280-1-sebastian.reichel@collabora.com> <20210428222953.235280-2-sebastian.reichel@collabora.com> In-Reply-To: <20210428222953.235280-2-sebastian.reichel@collabora.com> From: Saravana Kannan Date: Wed, 28 Apr 2021 18:11:10 -0700 Message-ID: Subject: Re: [PATCHv2 1/5] rtc: m41t80: add support for fixed clock To: Sebastian Reichel Cc: Philipp Zabel , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Rob Herring , Alexandre Belloni , Alessandro Zummo , David Airlie , Daniel Vetter , Miquel Raynal , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , dri-devel , linux-arm-kernel , LKML , linux-rtc@vger.kernel.org, linux-mtd@lists.infradead.org, Collabora Kernel ML X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210428_181148_978358_1A1ECC3F X-CRM114-Status: GOOD ( 28.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 28, 2021 at 3:29 PM Sebastian Reichel wrote: > > Congatec's QMX6 system on module (SoM) uses a m41t62 as RTC. The > modules SQW clock output defaults to 32768 Hz. This behaviour is > used to provide the i.MX6 CKIL clock. Once the RTC driver is probed, > the clock is disabled and all i.MX6 functionality depending on > the 32 KHz clock has undefined behaviour. For example when using > the hardware watchdog the system will likely do arbitrary reboots. > > Referencing the m41t62 directly results in a deadlock. The kernel > will see, that i.MX6 system clock needs the RTC clock and do probe > deferral. But the i.MX6 I2C module never becomes usable without the > i.MX6 CKIL clock and thus the RTC's clock will not be probed. So > from the kernel's perspective this is a chicken-and-egg problem. > > Technically everything is fine by not touching anything, since > the RTC clock correctly enables the clock on reset (i.e. on > battery backup power loss) and also the bootloader enables it > in case an something (e.g. an unpatched kernel) disabled this > incorrectly. > > A workaround for this issue is describing the square wave pin > as fixed-clock, which is registered early and basically how > this pin is used on the i.MX6. > > Suggested-by: Saravana Kannan > Signed-off-by: Sebastian Reichel > --- > Documentation/devicetree/bindings/rtc/rtc-m41t80.txt | 9 +++++++++ > drivers/rtc/rtc-m41t80.c | 12 ++++++++++++ > 2 files changed, 21 insertions(+) > > diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > index c746cb221210..cdd196b1e9bd 100644 > --- a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > +++ b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > @@ -21,10 +21,19 @@ Optional properties: > clock name > - wakeup-source: Enables wake up of host system on alarm > > +Optional child node: > +- clock: Provide this if the square wave pin is used as boot-enabled fixed clock. > + > Example: > rtc@68 { > compatible = "st,m41t80"; > reg = <0x68>; > interrupt-parent = <&UIC0>; > interrupts = <0x9 0x8>; > + > + clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + }; > }; > diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c > index 89128fc29ccc..b3ece42b6f90 100644 > --- a/drivers/rtc/rtc-m41t80.c > +++ b/drivers/rtc/rtc-m41t80.c > @@ -544,10 +544,22 @@ static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80) > { > struct i2c_client *client = m41t80->client; > struct device_node *node = client->dev.of_node; > + struct device_node *fixed_clock; > struct clk *clk; > struct clk_init_data init; > int ret; > > + fixed_clock = of_get_child_by_name(node, "clock"); > + if (fixed_clock) { > + /* > + * skip registering square wave clock when a fixed > + * clock has been registered. The fixed clock is > + * registered automatically when being referenced. > + */ > + of_node_put(fixed_clock); > + return 0; > + } > + > /* First disable the clock */ > ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); > if (ret < 0) Reviewed-by: Saravana Kannan -Saravana _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1A49C433ED for ; Thu, 29 Apr 2021 05:50:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7FCB061418 for ; Thu, 29 Apr 2021 05:50:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7FCB061418 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 17C756EC7B; Thu, 29 Apr 2021 05:49:53 +0000 (UTC) Received: from mail-yb1-xb31.google.com (mail-yb1-xb31.google.com [IPv6:2607:f8b0:4864:20::b31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B63D6ECE0 for ; Thu, 29 Apr 2021 01:11:47 +0000 (UTC) Received: by mail-yb1-xb31.google.com with SMTP id i4so38798601ybe.2 for ; Wed, 28 Apr 2021 18:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=B9WmxfQPgVB/G8qqdqqrH4JxR1XC119NUyqOOtSd7t0=; b=pkiPHPNLc8oPY1Rpg9s6MMH9zsVYb3Pu6hknNjJ97Hfi1mRnSBTaBnKpkK1xFjd1Qc cQcOSKlv6GspGLFBVFS0a2R7wfDy66R5CFpgbbx4KptsbtihfP16CiZn9rhGgXqx5QTW bT7wJSVgy86XNC/E1yQdfItBAZhtztfAwi05/r0kJhF9SMDdROLy1hNoB4qjsCCc7xWl mnFO4W/wNfSaDiAaT4Hzi7/2XKbK/+nwY+9Li/v4xqODqdRq+++/zwuK2aVSJ6jeZ06F W59O7/MT/99ty+gNnLuDf32EQ5etfkSEubBJ3iZEk34moqDnV4u5QwEcMfSvrieB519k avQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=B9WmxfQPgVB/G8qqdqqrH4JxR1XC119NUyqOOtSd7t0=; b=jEqtX+H6JeJnjQXANeow3iaF9HowQybuLMTYQQEjTeNxxf9POMIX5RDnGCpQSBXsRU NXd3e/sw+ZEm6WCeaXLxWyMjoalUK+GrzV8llF3hnuGcllaRwqBG4AYvX3k9B9DgEpmL wRojZZ7FOhLTNKJ8gQITEsTcmDgoauWv8Mnmef9MtRN3WLPVSVnXC/dVwFrgFTcPqDGy EM1bm85r0FYQWiWvIH/b9+wWDC7tOuKHQSJgaXwzbPUheUnj5WqQ5fh+DLlerxTZo/y+ MjABlVE8ZIfj3Q3zi0aZoUS0cizoo21LWPzTKJZSYzQjymAnyiBReHXD8YKDcmiXAsOU Pp6g== X-Gm-Message-State: AOAM5320oeR8ObhqdRzeY35ZadG2WfSlk/NCz6c4Nj366/fD/vL/CQX4 4BQ+51FNEsDeRwx+TcsIZsUQzVUFVgk+l7/MyNfTbg== X-Google-Smtp-Source: ABdhPJzGFBnav+DZBGGJcieg9JxgTULrcj3YfzoYD2uRXeNcTYI7rbQImezTdi5sUdA9XukgcMPYmupPisXhoBxFVf8= X-Received: by 2002:a25:58d5:: with SMTP id m204mr47013043ybb.32.1619658706418; Wed, 28 Apr 2021 18:11:46 -0700 (PDT) MIME-Version: 1.0 References: <20210428222953.235280-1-sebastian.reichel@collabora.com> <20210428222953.235280-2-sebastian.reichel@collabora.com> In-Reply-To: <20210428222953.235280-2-sebastian.reichel@collabora.com> From: Saravana Kannan Date: Wed, 28 Apr 2021 18:11:10 -0700 Message-ID: Subject: Re: [PATCHv2 1/5] rtc: m41t80: add support for fixed clock To: Sebastian Reichel X-Mailman-Approved-At: Thu, 29 Apr 2021 05:49:49 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rtc@vger.kernel.org, Alessandro Zummo , Alexandre Belloni , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , David Airlie , Shawn Guo , Sascha Hauer , LKML , dri-devel , Rob Herring , linux-mtd@lists.infradead.org, NXP Linux Team , Pengutronix Kernel Team , Miquel Raynal , Collabora Kernel ML , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Apr 28, 2021 at 3:29 PM Sebastian Reichel wrote: > > Congatec's QMX6 system on module (SoM) uses a m41t62 as RTC. The > modules SQW clock output defaults to 32768 Hz. This behaviour is > used to provide the i.MX6 CKIL clock. Once the RTC driver is probed, > the clock is disabled and all i.MX6 functionality depending on > the 32 KHz clock has undefined behaviour. For example when using > the hardware watchdog the system will likely do arbitrary reboots. > > Referencing the m41t62 directly results in a deadlock. The kernel > will see, that i.MX6 system clock needs the RTC clock and do probe > deferral. But the i.MX6 I2C module never becomes usable without the > i.MX6 CKIL clock and thus the RTC's clock will not be probed. So > from the kernel's perspective this is a chicken-and-egg problem. > > Technically everything is fine by not touching anything, since > the RTC clock correctly enables the clock on reset (i.e. on > battery backup power loss) and also the bootloader enables it > in case an something (e.g. an unpatched kernel) disabled this > incorrectly. > > A workaround for this issue is describing the square wave pin > as fixed-clock, which is registered early and basically how > this pin is used on the i.MX6. > > Suggested-by: Saravana Kannan > Signed-off-by: Sebastian Reichel > --- > Documentation/devicetree/bindings/rtc/rtc-m41t80.txt | 9 +++++++++ > drivers/rtc/rtc-m41t80.c | 12 ++++++++++++ > 2 files changed, 21 insertions(+) > > diff --git a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > index c746cb221210..cdd196b1e9bd 100644 > --- a/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > +++ b/Documentation/devicetree/bindings/rtc/rtc-m41t80.txt > @@ -21,10 +21,19 @@ Optional properties: > clock name > - wakeup-source: Enables wake up of host system on alarm > > +Optional child node: > +- clock: Provide this if the square wave pin is used as boot-enabled fixed clock. > + > Example: > rtc@68 { > compatible = "st,m41t80"; > reg = <0x68>; > interrupt-parent = <&UIC0>; > interrupts = <0x9 0x8>; > + > + clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + }; > }; > diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c > index 89128fc29ccc..b3ece42b6f90 100644 > --- a/drivers/rtc/rtc-m41t80.c > +++ b/drivers/rtc/rtc-m41t80.c > @@ -544,10 +544,22 @@ static struct clk *m41t80_sqw_register_clk(struct m41t80_data *m41t80) > { > struct i2c_client *client = m41t80->client; > struct device_node *node = client->dev.of_node; > + struct device_node *fixed_clock; > struct clk *clk; > struct clk_init_data init; > int ret; > > + fixed_clock = of_get_child_by_name(node, "clock"); > + if (fixed_clock) { > + /* > + * skip registering square wave clock when a fixed > + * clock has been registered. The fixed clock is > + * registered automatically when being referenced. > + */ > + of_node_put(fixed_clock); > + return 0; > + } > + > /* First disable the clock */ > ret = i2c_smbus_read_byte_data(client, M41T80_REG_ALARM_MON); > if (ret < 0) Reviewed-by: Saravana Kannan -Saravana _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel