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From: Daniel Kurtz <djkurtz@chromium.org>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>,
	Keith Packard <keithp@keithp.com>,
	David Airlie <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	Benson Leung <bleung@chromium.org>,
	Yufeng Shen <miletus@chromium.org>
Subject: Re: [PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes
Date: Thu, 29 Mar 2012 16:46:39 +0800	[thread overview]
Message-ID: <CAGS+omBkrjdrweGxS5r7KFyqx=JFVxy7_tqZsWTaGgfXu-VgtQ@mail.gmail.com> (raw)
In-Reply-To: <1332960093_131068@CP5-2952>

On Thu, Mar 29, 2012 at 2:41 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote:
>> The GMBUS controller GMBUS3 register is double-buffered.  Take advantage
>> of this  by writing two 4-byte words before the first wait for HW_RDY.
>> This helps keep the GMBUS controller from becoming idle during long writes.
>>
>> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
>
> "For byte counts that are greater than four bytes, this register will be
> written with subsequent data only after the HW_RDY status bit is set"
>
> Hmm, I had interpretted that as should only be. But if you take into
> account that the register is indeed double-buffered, it does make sense
> that the hardware itself is only updated after the HW_RDY signal.
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

In fact, during my experiments using the GMBUS interrupts, the HW_RDY
interrupt would only trigger for transactions > 4 bytes after 2 writes
to GMBUS3.


> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre

  reply	other threads:[~2012-03-29  8:47 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-28 18:26 [PATCH 0/7 v6] fix gmbus writes and related issues Daniel Kurtz
2012-03-28 18:26 ` [PATCH 1/7 v6] drm/i915/intel_i2c: handle zero-length writes Daniel Kurtz
2012-03-28 18:34   ` Chris Wilson
2012-03-28 18:34     ` Chris Wilson
2012-03-28 18:26 ` [PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes Daniel Kurtz
2012-03-28 18:41   ` Chris Wilson
2012-03-28 18:41     ` Chris Wilson
2012-03-29  8:46     ` Daniel Kurtz [this message]
2012-03-29  9:15       ` Daniel Vetter
2012-03-28 18:26 ` [PATCH 3/7 v6] drm/i915/intel_i2c: always wait for IDLE before clearing NAK Daniel Kurtz
2012-03-28 18:26 ` [PATCH 4/7 v6] drm/i915/intel_i2c: use WAIT cycle, not STOP Daniel Kurtz
2012-03-28 18:48   ` Chris Wilson
2012-03-28 18:48     ` Chris Wilson
2012-03-29  8:39     ` Daniel Kurtz
2012-03-28 18:26 ` [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions Daniel Kurtz
2012-03-28 18:52   ` Chris Wilson
2012-03-28 18:52     ` Chris Wilson
2012-03-29  8:37     ` Daniel Kurtz
2012-03-29  9:25       ` Daniel Vetter
2012-03-28 18:26 ` [PATCH 6/7 v6] drm/i915/intel_i2c: reuse GMBUS2 value read in polling loop Daniel Kurtz
2012-03-28 18:53   ` Chris Wilson
2012-03-28 18:53     ` Chris Wilson
2012-03-28 18:26 ` [PATCH 7/7 v6] drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers Daniel Kurtz
2012-03-28 18:53   ` Chris Wilson
2012-03-28 18:53     ` Chris Wilson

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