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* [PATCH 0/2] MT8173 clock changes for DRM
@ 2015-11-19 15:59 Philipp Zabel
  2015-11-19 15:59 ` [PATCH 1/2] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes Philipp Zabel
  2015-11-19 15:59 ` [PATCH 2/2] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output Philipp Zabel
  0 siblings, 2 replies; 4+ messages in thread
From: Philipp Zabel @ 2015-11-19 15:59 UTC (permalink / raw)
  To: Michael Turquette
  Cc: Stephen Boyd, Matthias Brugger, James Liao, Daniel Kurtz, Joe.C,
	kernel, linux-clk, linux-mediatek, Philipp Zabel

Hi,

I have sent these two as part of the MT8173 DRM/KMS driver patch series [1],
but not yet to the clock list. I'd be happy to get some review and
suggestions on how to best merge them, given the dependency of the DRM/KMS
driver on these changes.

[1] http://www.spinics.net/lists/dri-devel/msg94500.html

best regards
Philipp

Philipp Zabel (2):
  clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
  clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output

 drivers/clk/mediatek/clk-mt8173.c      | 9 +++++++--
 drivers/clk/mediatek/clk-mtk.h         | 7 +++++--
 include/dt-bindings/clock/mt8173-clk.h | 3 ++-
 3 files changed, 14 insertions(+), 5 deletions(-)

-- 
2.6.2

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 1/2] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
  2015-11-19 15:59 [PATCH 0/2] MT8173 clock changes for DRM Philipp Zabel
@ 2015-11-19 15:59 ` Philipp Zabel
  2015-11-20  0:56   ` Daniel Kurtz
  2015-11-19 15:59 ` [PATCH 2/2] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output Philipp Zabel
  1 sibling, 1 reply; 4+ messages in thread
From: Philipp Zabel @ 2015-11-19 15:59 UTC (permalink / raw)
  To: Michael Turquette
  Cc: Stephen Boyd, Matthias Brugger, James Liao, Daniel Kurtz, Joe.C,
	kernel, linux-clk, linux-mediatek, Philipp Zabel

These muxes are supposed to select a fitting divider after the PLL
is already set to the correct rate.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 drivers/clk/mediatek/clk-mt8173.c | 4 ++--
 drivers/clk/mediatek/clk-mtk.h    | 7 +++++--
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 227e356..b305fa2 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -558,7 +558,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
 	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
 	MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
 	/* CLK_CFG_6 */
-	MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
+	MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
 	MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
 	MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
 	MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
@@ -569,7 +569,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
 	MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
 	/* CLK_CFG_12 */
 	MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
-	MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
+	MUX_GATE_FLAGS(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15, 0),
 	MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
 	/* CLK_CFG_13 */
 	MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 32d2e45..b607996 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -83,7 +83,7 @@ struct mtk_composite {
 	signed char num_parents;
 };
 
-#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) {	\
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) {	\
 		.id = _id,						\
 		.name = _name,						\
 		.mux_reg = _reg,					\
@@ -94,9 +94,12 @@ struct mtk_composite {
 		.divider_shift = -1,					\
 		.parent_names = _parents,				\
 		.num_parents = ARRAY_SIZE(_parents),			\
-		.flags = CLK_SET_RATE_PARENT,				\
+		.flags = _flags,					\
 	}
 
+#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)	\
+	MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
+
 #define MUX(_id, _name, _parents, _reg, _shift, _width) {		\
 		.id = _id,						\
 		.name = _name,						\
-- 
2.6.2

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH 2/2] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
  2015-11-19 15:59 [PATCH 0/2] MT8173 clock changes for DRM Philipp Zabel
  2015-11-19 15:59 ` [PATCH 1/2] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes Philipp Zabel
@ 2015-11-19 15:59 ` Philipp Zabel
  1 sibling, 0 replies; 4+ messages in thread
From: Philipp Zabel @ 2015-11-19 15:59 UTC (permalink / raw)
  To: Michael Turquette
  Cc: Stephen Boyd, Matthias Brugger, James Liao, Daniel Kurtz, Joe.C,
	kernel, linux-clk, linux-mediatek, Philipp Zabel

The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 drivers/clk/mediatek/clk-mt8173.c      | 5 +++++
 include/dt-bindings/clock/mt8173-clk.h | 3 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index b305fa2..d7eadda 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -1091,6 +1091,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
 		clk_data->clks[cku->id] = clk;
 	}
 
+	clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
+				   base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
+				   NULL);
+	clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
+
 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 	if (r)
 		pr_err("%s(): could not register clock provider: %d\n",
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 7956ba1..6094bf7 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -176,7 +176,8 @@
 #define CLK_APMIXED_LVDSPLL		13
 #define CLK_APMIXED_MSDCPLL2		14
 #define CLK_APMIXED_REF2USB_TX		15
-#define CLK_APMIXED_NR_CLK		16
+#define CLK_APMIXED_HDMI_REF		16
+#define CLK_APMIXED_NR_CLK		17
 
 /* INFRA_SYS */
 
-- 
2.6.2

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH 1/2] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes
  2015-11-19 15:59 ` [PATCH 1/2] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes Philipp Zabel
@ 2015-11-20  0:56   ` Daniel Kurtz
  0 siblings, 0 replies; 4+ messages in thread
From: Daniel Kurtz @ 2015-11-20  0:56 UTC (permalink / raw)
  To: Philipp Zabel, Douglas Anderson, Heiko Stübner
  Cc: Michael Turquette, Stephen Boyd, Matthias Brugger, James Liao,
	Joe.C, Sasha Hauer, linux-clk, linux-mediatek, Caesar Wang

+Heiko and +dianders who worked so hard to get the multi-stage HDMI
clocks behaving well for the rk3288.

On Thu, Nov 19, 2015 at 11:59 PM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> These muxes are supposed to select a fitting divider after the PLL
> is already set to the correct rate.
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
>  drivers/clk/mediatek/clk-mt8173.c | 4 ++--
>  drivers/clk/mediatek/clk-mtk.h    | 7 +++++--
>  2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
> index 227e356..b305fa2 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -558,7 +558,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
>         MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
>         MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
>         /* CLK_CFG_6 */
> -       MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
> +       MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
>         MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
>         MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
>         MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
> @@ -569,7 +569,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
>         MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
>         /* CLK_CFG_12 */
>         MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
> -       MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
> +       MUX_GATE_FLAGS(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15, 0),
>         MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
>         /* CLK_CFG_13 */
>         MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 32d2e45..b607996 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -83,7 +83,7 @@ struct mtk_composite {
>         signed char num_parents;
>  };
>
> -#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) {  \
> +#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) {    \
>                 .id = _id,                                              \
>                 .name = _name,                                          \
>                 .mux_reg = _reg,                                        \
> @@ -94,9 +94,12 @@ struct mtk_composite {
>                 .divider_shift = -1,                                    \
>                 .parent_names = _parents,                               \
>                 .num_parents = ARRAY_SIZE(_parents),                    \
> -               .flags = CLK_SET_RATE_PARENT,                           \
> +               .flags = _flags,                                        \
>         }
>
> +#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)    \
> +       MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
> +
>  #define MUX(_id, _name, _parents, _reg, _shift, _width) {              \
>                 .id = _id,                                              \
>                 .name = _name,                                          \
> --
> 2.6.2
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2015-11-20  0:56 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-11-19 15:59 [PATCH 0/2] MT8173 clock changes for DRM Philipp Zabel
2015-11-19 15:59 ` [PATCH 1/2] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes Philipp Zabel
2015-11-20  0:56   ` Daniel Kurtz
2015-11-19 15:59 ` [PATCH 2/2] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output Philipp Zabel

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