From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kees Cook Subject: Re: x86: PIE support and option to extend KASLR randomization Date: Fri, 22 Sep 2017 11:57:09 -0700 Message-ID: References: <20170816151235.oamkdva6cwpc4cex@gmail.com> <20170817080920.5ljlkktngw2cisfg@gmail.com> <20170825080443.tvvr6wzs362cjcuu@gmail.com> <20170921155919.skpyt7dutod5ul4t@gmail.com> <20170922163225.bfrd5myl6d7deiim@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Cc: Ingo Molnar , Thomas Garnier , Herbert Xu , "David S . Miller" , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Josh Poimboeuf , Arnd Bergmann , Matthias Kaehlcke , Boris Ostrovsky , Juergen Gross , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Joerg Roedel , Tom Lendacky , Andy Lutomirski , Borislav Petkov , Brian Gerst , "Kirill A . Shutemov" , "Rafael J . Wysocki" , Len Brown , Pavel Machek , Teju To: "H. Peter Anvin" Return-path: List-Post: List-Help: List-Unsubscribe: List-Subscribe: Sender: keescook@google.com In-Reply-To: List-Id: linux-crypto.vger.kernel.org On Fri, Sep 22, 2017 at 11:38 AM, H. Peter Anvin wrote: > We lose EBX on 32 bits, but we don't lose RBX on 64 bits - since x86-64 > has RIP-relative addressing there is no need for a dedicated PIC register. FWIW, since gcc 5, the PIC register isn't totally lost. It is now reusable, and that seems to have improved performance: https://gcc.gnu.org/gcc-5/changes.html -Kees -- Kees Cook Pixel Security From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 Sender: keescook@google.com In-Reply-To: References: <20170816151235.oamkdva6cwpc4cex@gmail.com> <20170817080920.5ljlkktngw2cisfg@gmail.com> <20170825080443.tvvr6wzs362cjcuu@gmail.com> <20170921155919.skpyt7dutod5ul4t@gmail.com> <20170922163225.bfrd5myl6d7deiim@gmail.com> From: Kees Cook Date: Fri, 22 Sep 2017 11:57:09 -0700 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: [kernel-hardening] Re: x86: PIE support and option to extend KASLR randomization To: "H. Peter Anvin" Cc: Ingo Molnar , Thomas Garnier , Herbert Xu , "David S . Miller" , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Josh Poimboeuf , Arnd Bergmann , Matthias Kaehlcke , Boris Ostrovsky , Juergen Gross , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Joerg Roedel , Tom Lendacky , Andy Lutomirski , Borislav Petkov , Brian Gerst , "Kirill A . Shutemov" , "Rafael J . Wysocki" , Len Brown , Pavel Machek , Tejun Heo , Christoph Lameter , Paul Gortmaker , Chris Metcalf , Andrew Morton , "Paul E . McKenney" , Nicolas Pitre , Christopher Li , "Rafael J . Wysocki" , Lukas Wunner , Mika Westerberg , Dou Liyang , Daniel Borkmann , Alexei Starovoitov , Masahiro Yamada , Markus Trippelsdorf , Steven Rostedt , Rik van Riel , David Howells , Waiman Long , Kyle Huey , Peter Foley , Tim Chen , Catalin Marinas , Ard Biesheuvel , Michal Hocko , Matthew Wilcox , "H . J . Lu" , Paul Bolle , Rob Landley , Baoquan He , Daniel Micay , the arch/x86 maintainers , Linux Crypto Mailing List , LKML , xen-devel , kvm list , Linux PM list , linux-arch , Sparse Mailing-list , Kernel Hardening , Linus Torvalds , Peter Zijlstra , Borislav Petkov List-ID: On Fri, Sep 22, 2017 at 11:38 AM, H. Peter Anvin wrote: > We lose EBX on 32 bits, but we don't lose RBX on 64 bits - since x86-64 > has RIP-relative addressing there is no need for a dedicated PIC register. FWIW, since gcc 5, the PIC register isn't totally lost. It is now reusable, and that seems to have improved performance: https://gcc.gnu.org/gcc-5/changes.html -Kees -- Kees Cook Pixel Security