From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753846AbbESHMk (ORCPT ); Tue, 19 May 2015 03:12:40 -0400 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:51619 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752665AbbESHMh (ORCPT ); Tue, 19 May 2015 03:12:37 -0400 MIME-Version: 1.0 In-Reply-To: <20150517145146.GK4004@lukather> References: <1431583811-25780-1-git-send-email-wens@csie.org> <1431583811-25780-3-git-send-email-wens@csie.org> <20150517145146.GK4004@lukather> From: Chen-Yu Tsai Date: Tue, 19 May 2015 15:12:11 +0800 Message-ID: Subject: Re: [RFC 2/7] ARM: dts: sun9i: Add CCI-400 device nodes for A80 To: Maxime Ripard Cc: Chen-Yu Tsai , Nicolas Pitre , Dave Martin , linux-arm-kernel , linux-kernel , linux-sunxi Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, May 17, 2015 at 10:51 PM, Maxime Ripard wrote: > On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote: >> The A80 includes an ARM CCI-400 interconnect to support multi-cluster >> CPU caches. >> >> Also add the default clock frequency for the CPUs. >> >> Signed-off-by: Chen-Yu Tsai >> --- >> arch/arm/boot/dts/sun9i-a80.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi >> index ca272e92b85d..200e712fbf0e 100644 >> --- a/arch/arm/boot/dts/sun9i-a80.dtsi >> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi >> @@ -58,48 +58,64 @@ >> cpu0: cpu@0 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x0>; >> }; >> >> cpu1: cpu@1 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x1>; >> }; >> >> cpu2: cpu@2 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x2>; >> }; >> >> cpu3: cpu@3 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x3>; >> }; >> >> cpu4: cpu@100 { >> compatible = "arm,cortex-a15"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control1>; >> + clock-frequency = <9000000>; > > Isn't the clock frequency property is supposed to be the maximum > frequency of that CPU in Linux? > > It looks odd that the A15 are clocked at a lower frequency than the > A7... You're right. Looking at the FEX file, the A15s can go up to 1.8 GHz. I'll update the numbers. ChenYu From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Tue, 19 May 2015 15:12:11 +0800 Subject: [RFC 2/7] ARM: dts: sun9i: Add CCI-400 device nodes for A80 In-Reply-To: <20150517145146.GK4004@lukather> References: <1431583811-25780-1-git-send-email-wens@csie.org> <1431583811-25780-3-git-send-email-wens@csie.org> <20150517145146.GK4004@lukather> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sun, May 17, 2015 at 10:51 PM, Maxime Ripard wrote: > On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote: >> The A80 includes an ARM CCI-400 interconnect to support multi-cluster >> CPU caches. >> >> Also add the default clock frequency for the CPUs. >> >> Signed-off-by: Chen-Yu Tsai >> --- >> arch/arm/boot/dts/sun9i-a80.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi >> index ca272e92b85d..200e712fbf0e 100644 >> --- a/arch/arm/boot/dts/sun9i-a80.dtsi >> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi >> @@ -58,48 +58,64 @@ >> cpu0: cpu at 0 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x0>; >> }; >> >> cpu1: cpu at 1 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x1>; >> }; >> >> cpu2: cpu at 2 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x2>; >> }; >> >> cpu3: cpu at 3 { >> compatible = "arm,cortex-a7"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control0>; >> + clock-frequency = <12000000>; >> reg = <0x3>; >> }; >> >> cpu4: cpu at 100 { >> compatible = "arm,cortex-a15"; >> device_type = "cpu"; >> + cci-control-port = <&cci_control1>; >> + clock-frequency = <9000000>; > > Isn't the clock frequency property is supposed to be the maximum > frequency of that CPU in Linux? > > It looks odd that the A15 are clocked at a lower frequency than the > A7... You're right. Looking at the FEX file, the A15s can go up to 1.8 GHz. I'll update the numbers. ChenYu