From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C929C433FF for ; Mon, 29 Jul 2019 06:43:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0628D2075B for ; Mon, 29 Jul 2019 06:43:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726951AbfG2Gnk convert rfc822-to-8bit (ORCPT ); Mon, 29 Jul 2019 02:43:40 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:46603 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726088AbfG2Gnj (ORCPT ); Mon, 29 Jul 2019 02:43:39 -0400 Received: by mail-ed1-f65.google.com with SMTP id d4so58318304edr.13; Sun, 28 Jul 2019 23:43:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=N3YcfI6Lt3N7Xfg/QsppatAiaJc9l2mfK7jxMUvJqWY=; b=ruNZ5YEUBG1D0cBfLarMvvTPCOfzNNKXypaliIhjwTzBAs1Rr3RR3XReoWXR3SubIh MtTwXxz2GK/waoekFOnXYASQPzOb7oO22PesxnksVL06DuWhu5YxiNVkW/aC1PEwZwD0 l2wxET4OQzELqOEkZpmtUBjWbse9ncHzmzr9k2hvcGPMQxipjbJKuTDOM501l0qqTHB/ vq1umPUpOAOw5Bkkj8Caexq/AmARqElWcg50cpLqU1+QpINNs8ohZZXjFm2io7Jm5Iph vwfaijClkYbtl5W++ATAWFKnIv1E4GP4iZjQsBS4Oqi2KYcVidiMel/XBG2of67bNjbv NQ3g== X-Gm-Message-State: APjAAAVxN7dlJF8qDGCQPuOaoUZqU4LyJkRWmhcm/SO9YMxjKVT+LLV6 GtDH2XCrK3GoPfhqwPh6yFmxENtGEnk= X-Google-Smtp-Source: APXvYqzFdJFRI/52u5fOHTiP8mLDcJ4ShMlNVqfK+Uef0oXPRqygtDeBly8v6e3OscHYonJ6nylk+Q== X-Received: by 2002:a17:906:3497:: with SMTP id g23mr83306443ejb.70.1564382617102; Sun, 28 Jul 2019 23:43:37 -0700 (PDT) Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com. [209.85.221.50]) by smtp.gmail.com with ESMTPSA id f36sm15796131ede.47.2019.07.28.23.43.36 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Sun, 28 Jul 2019 23:43:36 -0700 (PDT) Received: by mail-wr1-f50.google.com with SMTP id r1so60460548wrl.7; Sun, 28 Jul 2019 23:43:36 -0700 (PDT) X-Received: by 2002:adf:e941:: with SMTP id m1mr30982207wrn.279.1564382616355; Sun, 28 Jul 2019 23:43:36 -0700 (PDT) MIME-Version: 1.0 References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-3-jernej.skrabec@siol.net> <20190729063630.rn325whatfnc3m7n@pengutronix.de> In-Reply-To: <20190729063630.rn325whatfnc3m7n@pengutronix.de> From: Chen-Yu Tsai Date: Mon, 29 Jul 2019 14:43:23 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/6] pwm: sun4i: Add a quirk for reset line To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= Cc: Jernej Skrabec , Thierry Reding , Maxime Ripard , Rob Herring , Mark Rutland , linux-pwm@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi , Philipp Zabel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 29, 2019 at 2:36 PM Uwe Kleine-König wrote: > > Cc += reset framework maintainer > > Hello Jernej, > > On Fri, Jul 26, 2019 at 08:40:41PM +0200, Jernej Skrabec wrote: > > H6 PWM core needs deasserted reset line in order to work. > > > > Add a quirk for it. > > > > Signed-off-by: Jernej Skrabec > > --- > > drivers/pwm/pwm-sun4i.c | 27 +++++++++++++++++++++++++-- > > 1 file changed, 25 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index de78c824bbfd..1b7be8fbde86 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -16,6 +16,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -72,12 +73,14 @@ static const u32 prescaler_table[] = { > > > > struct sun4i_pwm_data { > > bool has_prescaler_bypass; > > + bool has_reset; > > unsigned int npwm; > > }; > > > > struct sun4i_pwm_chip { > > struct pwm_chip chip; > > struct clk *clk; > > + struct reset_control *rst; > > void __iomem *base; > > spinlock_t ctrl_lock; > > const struct sun4i_pwm_data *data; > > @@ -371,6 +374,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > if (IS_ERR(pwm->clk)) > > return PTR_ERR(pwm->clk); > > > > + if (pwm->data->has_reset) { > > + pwm->rst = devm_reset_control_get(&pdev->dev, NULL); > > + if (IS_ERR(pwm->rst)) > > + return PTR_ERR(pwm->rst); > > + > > + reset_control_deassert(pwm->rst); > > + } > > + > > I wonder why there is a need to track if a given chip needs a reset > line. I'd just use devm_reset_control_get_optional() and drop the > .has_reset member in struct sun4i_pwm_data. Because it's not optional for this platform, i.e. it won't work if the reset control (or clk, in the next patch) is somehow missing from the device tree. ChenYu > > pwm->chip.dev = &pdev->dev; > > pwm->chip.ops = &sun4i_pwm_ops; > > pwm->chip.base = -1; > > @@ -383,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > ret = pwmchip_add(&pwm->chip); > > if (ret < 0) { > > dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); > > - return ret; > > + goto err_pwm_add; > > } > > > > platform_set_drvdata(pdev, pwm); > > > > return 0; > > + > > +err_pwm_add: > > + reset_control_assert(pwm->rst); > > + > > + return ret; > > } > > > > static int sun4i_pwm_remove(struct platform_device *pdev) > > { > > struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); > > + int ret; > > + > > + ret = pwmchip_remove(&pwm->chip); > > + if (ret) > > + return ret; > > > > - return pwmchip_remove(&pwm->chip); > > + reset_control_assert(pwm->rst); > > + > > + return 0; > > } > > > > static struct platform_driver sun4i_pwm_driver = { > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | http://www.pengutronix.de/ | From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCH 2/6] pwm: sun4i: Add a quirk for reset line Date: Mon, 29 Jul 2019 14:43:23 +0800 Message-ID: References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-3-jernej.skrabec@siol.net> <20190729063630.rn325whatfnc3m7n@pengutronix.de> Reply-To: wens-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190729063630.rn325whatfnc3m7n-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= Cc: Jernej Skrabec , Thierry Reding , Maxime Ripard , Rob Herring , Mark Rutland , linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi , Philipp Zabel List-Id: devicetree@vger.kernel.org On Mon, Jul 29, 2019 at 2:36 PM Uwe Kleine-K=C3=B6nig wrote: > > Cc +=3D reset framework maintainer > > Hello Jernej, > > On Fri, Jul 26, 2019 at 08:40:41PM +0200, Jernej Skrabec wrote: > > H6 PWM core needs deasserted reset line in order to work. > > > > Add a quirk for it. > > > > Signed-off-by: Jernej Skrabec > > --- > > drivers/pwm/pwm-sun4i.c | 27 +++++++++++++++++++++++++-- > > 1 file changed, 25 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index de78c824bbfd..1b7be8fbde86 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -16,6 +16,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -72,12 +73,14 @@ static const u32 prescaler_table[] =3D { > > > > struct sun4i_pwm_data { > > bool has_prescaler_bypass; > > + bool has_reset; > > unsigned int npwm; > > }; > > > > struct sun4i_pwm_chip { > > struct pwm_chip chip; > > struct clk *clk; > > + struct reset_control *rst; > > void __iomem *base; > > spinlock_t ctrl_lock; > > const struct sun4i_pwm_data *data; > > @@ -371,6 +374,14 @@ static int sun4i_pwm_probe(struct platform_device = *pdev) > > if (IS_ERR(pwm->clk)) > > return PTR_ERR(pwm->clk); > > > > + if (pwm->data->has_reset) { > > + pwm->rst =3D devm_reset_control_get(&pdev->dev, NULL); > > + if (IS_ERR(pwm->rst)) > > + return PTR_ERR(pwm->rst); > > + > > + reset_control_deassert(pwm->rst); > > + } > > + > > I wonder why there is a need to track if a given chip needs a reset > line. I'd just use devm_reset_control_get_optional() and drop the > .has_reset member in struct sun4i_pwm_data. Because it's not optional for this platform, i.e. it won't work if the reset control (or clk, in the next patch) is somehow missing from the device tree. ChenYu > > pwm->chip.dev =3D &pdev->dev; > > pwm->chip.ops =3D &sun4i_pwm_ops; > > pwm->chip.base =3D -1; > > @@ -383,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device= *pdev) > > ret =3D pwmchip_add(&pwm->chip); > > if (ret < 0) { > > dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); > > - return ret; > > + goto err_pwm_add; > > } > > > > platform_set_drvdata(pdev, pwm); > > > > return 0; > > + > > +err_pwm_add: > > + reset_control_assert(pwm->rst); > > + > > + return ret; > > } > > > > static int sun4i_pwm_remove(struct platform_device *pdev) > > { > > struct sun4i_pwm_chip *pwm =3D platform_get_drvdata(pdev); > > + int ret; > > + > > + ret =3D pwmchip_remove(&pwm->chip); > > + if (ret) > > + return ret; > > > > - return pwmchip_remove(&pwm->chip); > > + reset_control_assert(pwm->rst); > > + > > + return 0; > > } > > > > static struct platform_driver sun4i_pwm_driver =3D { > > -- > Pengutronix e.K. | Uwe Kleine-K=C3=B6nig = | > Industrial Linux Solutions | http://www.pengutronix.de/ = | --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org To view this discussion on the web, visit https://groups.google.com/d/msgid= /linux-sunxi/CAGb2v65KOpivHQNkg%2BR2%3DD%3DejCJYnPdVcyHJZW-GJCR8j0Yk0g%40ma= il.gmail.com. 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[209.85.221.54]) by smtp.gmail.com with ESMTPSA id f26sm7792877ejo.25.2019.07.28.23.43.36 for (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Sun, 28 Jul 2019 23:43:36 -0700 (PDT) Received: by mail-wr1-f54.google.com with SMTP id 31so60505601wrm.1 for ; Sun, 28 Jul 2019 23:43:36 -0700 (PDT) X-Received: by 2002:adf:e941:: with SMTP id m1mr30982207wrn.279.1564382616355; Sun, 28 Jul 2019 23:43:36 -0700 (PDT) MIME-Version: 1.0 References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-3-jernej.skrabec@siol.net> <20190729063630.rn325whatfnc3m7n@pengutronix.de> In-Reply-To: <20190729063630.rn325whatfnc3m7n@pengutronix.de> From: Chen-Yu Tsai Date: Mon, 29 Jul 2019 14:43:23 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/6] pwm: sun4i: Add a quirk for reset line To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190728_234342_059472_D34E330B X-CRM114-Status: GOOD ( 22.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-pwm@vger.kernel.org, Jernej Skrabec , devicetree , linux-kernel , Maxime Ripard , linux-sunxi , Rob Herring , Thierry Reding , Philipp Zabel , linux-arm-kernel Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gTW9uLCBKdWwgMjksIDIwMTkgYXQgMjozNiBQTSBVd2UgS2xlaW5lLUvDtm5pZwo8dS5rbGVp bmUta29lbmlnQHBlbmd1dHJvbml4LmRlPiB3cm90ZToKPgo+IENjICs9IHJlc2V0IGZyYW1ld29y ayBtYWludGFpbmVyCj4KPiBIZWxsbyBKZXJuZWosCj4KPiBPbiBGcmksIEp1bCAyNiwgMjAxOSBh dCAwODo0MDo0MVBNICswMjAwLCBKZXJuZWogU2tyYWJlYyB3cm90ZToKPiA+IEg2IFBXTSBjb3Jl IG5lZWRzIGRlYXNzZXJ0ZWQgcmVzZXQgbGluZSBpbiBvcmRlciB0byB3b3JrLgo+ID4KPiA+IEFk ZCBhIHF1aXJrIGZvciBpdC4KPiA+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBKZXJuZWogU2tyYWJlYyA8 amVybmVqLnNrcmFiZWNAc2lvbC5uZXQ+Cj4gPiAtLS0KPiA+ICBkcml2ZXJzL3B3bS9wd20tc3Vu NGkuYyB8IDI3ICsrKysrKysrKysrKysrKysrKysrKysrKystLQo+ID4gIDEgZmlsZSBjaGFuZ2Vk LCAyNSBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQo+ID4KPiA+IGRpZmYgLS1naXQgYS9k cml2ZXJzL3B3bS9wd20tc3VuNGkuYyBiL2RyaXZlcnMvcHdtL3B3bS1zdW40aS5jCj4gPiBpbmRl eCBkZTc4YzgyNGJiZmQuLjFiN2JlOGZiZGU4NiAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvcHdt L3B3bS1zdW40aS5jCj4gPiArKysgYi9kcml2ZXJzL3B3bS9wd20tc3VuNGkuYwo+ID4gQEAgLTE2 LDYgKzE2LDcgQEAKPiA+ICAjaW5jbHVkZSA8bGludXgvb2ZfZGV2aWNlLmg+Cj4gPiAgI2luY2x1 ZGUgPGxpbnV4L3BsYXRmb3JtX2RldmljZS5oPgo+ID4gICNpbmNsdWRlIDxsaW51eC9wd20uaD4K PiA+ICsjaW5jbHVkZSA8bGludXgvcmVzZXQuaD4KPiA+ICAjaW5jbHVkZSA8bGludXgvc2xhYi5o Pgo+ID4gICNpbmNsdWRlIDxsaW51eC9zcGlubG9jay5oPgo+ID4gICNpbmNsdWRlIDxsaW51eC90 aW1lLmg+Cj4gPiBAQCAtNzIsMTIgKzczLDE0IEBAIHN0YXRpYyBjb25zdCB1MzIgcHJlc2NhbGVy X3RhYmxlW10gPSB7Cj4gPgo+ID4gIHN0cnVjdCBzdW40aV9wd21fZGF0YSB7Cj4gPiAgICAgICBi b29sIGhhc19wcmVzY2FsZXJfYnlwYXNzOwo+ID4gKyAgICAgYm9vbCBoYXNfcmVzZXQ7Cj4gPiAg ICAgICB1bnNpZ25lZCBpbnQgbnB3bTsKPiA+ICB9Owo+ID4KPiA+ICBzdHJ1Y3Qgc3VuNGlfcHdt X2NoaXAgewo+ID4gICAgICAgc3RydWN0IHB3bV9jaGlwIGNoaXA7Cj4gPiAgICAgICBzdHJ1Y3Qg Y2xrICpjbGs7Cj4gPiArICAgICBzdHJ1Y3QgcmVzZXRfY29udHJvbCAqcnN0Owo+ID4gICAgICAg dm9pZCBfX2lvbWVtICpiYXNlOwo+ID4gICAgICAgc3BpbmxvY2tfdCBjdHJsX2xvY2s7Cj4gPiAg ICAgICBjb25zdCBzdHJ1Y3Qgc3VuNGlfcHdtX2RhdGEgKmRhdGE7Cj4gPiBAQCAtMzcxLDYgKzM3 NCwxNCBAQCBzdGF0aWMgaW50IHN1bjRpX3B3bV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNl ICpwZGV2KQo+ID4gICAgICAgaWYgKElTX0VSUihwd20tPmNsaykpCj4gPiAgICAgICAgICAgICAg IHJldHVybiBQVFJfRVJSKHB3bS0+Y2xrKTsKPiA+Cj4gPiArICAgICBpZiAocHdtLT5kYXRhLT5o YXNfcmVzZXQpIHsKPiA+ICsgICAgICAgICAgICAgcHdtLT5yc3QgPSBkZXZtX3Jlc2V0X2NvbnRy b2xfZ2V0KCZwZGV2LT5kZXYsIE5VTEwpOwo+ID4gKyAgICAgICAgICAgICBpZiAoSVNfRVJSKHB3 bS0+cnN0KSkKPiA+ICsgICAgICAgICAgICAgICAgICAgICByZXR1cm4gUFRSX0VSUihwd20tPnJz dCk7Cj4gPiArCj4gPiArICAgICAgICAgICAgIHJlc2V0X2NvbnRyb2xfZGVhc3NlcnQocHdtLT5y c3QpOwo+ID4gKyAgICAgfQo+ID4gKwo+Cj4gSSB3b25kZXIgd2h5IHRoZXJlIGlzIGEgbmVlZCB0 byB0cmFjayBpZiBhIGdpdmVuIGNoaXAgbmVlZHMgYSByZXNldAo+IGxpbmUuIEknZCBqdXN0IHVz ZSBkZXZtX3Jlc2V0X2NvbnRyb2xfZ2V0X29wdGlvbmFsKCkgYW5kIGRyb3AgdGhlCj4gLmhhc19y ZXNldCBtZW1iZXIgaW4gc3RydWN0IHN1bjRpX3B3bV9kYXRhLgoKQmVjYXVzZSBpdCdzIG5vdCBv cHRpb25hbCBmb3IgdGhpcyBwbGF0Zm9ybSwgaS5lLiBpdCB3b24ndCB3b3JrIGlmCnRoZSByZXNl dCBjb250cm9sIChvciBjbGssIGluIHRoZSBuZXh0IHBhdGNoKSBpcyBzb21laG93IG1pc3Npbmcg ZnJvbQp0aGUgZGV2aWNlIHRyZWUuCgpDaGVuWXUKCj4gPiAgICAgICBwd20tPmNoaXAuZGV2ID0g JnBkZXYtPmRldjsKPiA+ICAgICAgIHB3bS0+Y2hpcC5vcHMgPSAmc3VuNGlfcHdtX29wczsKPiA+ ICAgICAgIHB3bS0+Y2hpcC5iYXNlID0gLTE7Cj4gPiBAQCAtMzgzLDE5ICszOTQsMzEgQEAgc3Rh dGljIGludCBzdW40aV9wd21fcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiA+ ICAgICAgIHJldCA9IHB3bWNoaXBfYWRkKCZwd20tPmNoaXApOwo+ID4gICAgICAgaWYgKHJldCA8 IDApIHsKPiA+ICAgICAgICAgICAgICAgZGV2X2VycigmcGRldi0+ZGV2LCAiZmFpbGVkIHRvIGFk ZCBQV00gY2hpcDogJWRcbiIsIHJldCk7Cj4gPiAtICAgICAgICAgICAgIHJldHVybiByZXQ7Cj4g PiArICAgICAgICAgICAgIGdvdG8gZXJyX3B3bV9hZGQ7Cj4gPiAgICAgICB9Cj4gPgo+ID4gICAg ICAgcGxhdGZvcm1fc2V0X2RydmRhdGEocGRldiwgcHdtKTsKPiA+Cj4gPiAgICAgICByZXR1cm4g MDsKPiA+ICsKPiA+ICtlcnJfcHdtX2FkZDoKPiA+ICsgICAgIHJlc2V0X2NvbnRyb2xfYXNzZXJ0 KHB3bS0+cnN0KTsKPiA+ICsKPiA+ICsgICAgIHJldHVybiByZXQ7Cj4gPiAgfQo+ID4KPiA+ICBz dGF0aWMgaW50IHN1bjRpX3B3bV9yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikK PiA+ICB7Cj4gPiAgICAgICBzdHJ1Y3Qgc3VuNGlfcHdtX2NoaXAgKnB3bSA9IHBsYXRmb3JtX2dl dF9kcnZkYXRhKHBkZXYpOwo+ID4gKyAgICAgaW50IHJldDsKPiA+ICsKPiA+ICsgICAgIHJldCA9 IHB3bWNoaXBfcmVtb3ZlKCZwd20tPmNoaXApOwo+ID4gKyAgICAgaWYgKHJldCkKPiA+ICsgICAg ICAgICAgICAgcmV0dXJuIHJldDsKPiA+Cj4gPiAtICAgICByZXR1cm4gcHdtY2hpcF9yZW1vdmUo JnB3bS0+Y2hpcCk7Cj4gPiArICAgICByZXNldF9jb250cm9sX2Fzc2VydChwd20tPnJzdCk7Cj4g PiArCj4gPiArICAgICByZXR1cm4gMDsKPiA+ICB9Cj4gPgo+ID4gIHN0YXRpYyBzdHJ1Y3QgcGxh dGZvcm1fZHJpdmVyIHN1bjRpX3B3bV9kcml2ZXIgPSB7Cj4KPiAtLQo+IFBlbmd1dHJvbml4IGUu Sy4gICAgICAgICAgICAgICAgICAgICAgICAgICB8IFV3ZSBLbGVpbmUtS8O2bmlnICAgICAgICAg ICAgfAo+IEluZHVzdHJpYWwgTGludXggU29sdXRpb25zICAgICAgICAgICAgICAgICB8IGh0dHA6 Ly93d3cucGVuZ3V0cm9uaXguZGUvICB8CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==