From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32823C4361B for ; Thu, 3 Dec 2020 16:45:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6FEB207AE for ; Thu, 3 Dec 2020 16:45:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2501861AbgLCQpT (ORCPT ); Thu, 3 Dec 2020 11:45:19 -0500 Received: from mail-lf1-f66.google.com ([209.85.167.66]:34711 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726026AbgLCQpS (ORCPT ); Thu, 3 Dec 2020 11:45:18 -0500 Received: by mail-lf1-f66.google.com with SMTP id d8so3699101lfa.1; Thu, 03 Dec 2020 08:45:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gSKKMnPPwvy/Gv2/NSqLNOEr9O1XfSpR38BNRVeZqQg=; b=R0NXaKKjBgzfvPUAvoKQUtO9dwisLyKf8qNq09HHDDiFpEYrmNQalQfuczPaAOvGE9 mkgR2+JIo3AyOcH8Y9C16lH90ggUnQEzzpCOYB5lQK8fp19VupQAD4ryLTcL6SZ3uP0E idab8U92HewBr9PMqqfdX/l6dAstb1fBCav1FwvC34iQz/Vgu+aQ854Y7T9G7M0p14+b Sc2ZaTiSQlAkEmm+c7MzeI3WJjFngDe2VXKTcud3BWK7db+n+mGwbjXhc3x2qC60Uv78 zE+22MWtP+/psNFIm8ZaNCDvvFtIXBIyvOUkG8POFVNQRRzR3tNun7n1QZS05yE1BiOG fncg== X-Gm-Message-State: AOAM5305huPCP4Rw0yM60r3IcIf1io9NMmd8Y03pi6VDHIGPNHOXgjol bwPIvG4jyGqdEZM3/RI2MTphgJxMM/5Ziw== X-Google-Smtp-Source: ABdhPJwxE4X/64DjbH+i3bspzyYxKRpi4Bx7iIvDgyyI1tP69HuTvmqBmdQZ6oWcs9ojvJy0Q9ADnQ== X-Received: by 2002:a19:348:: with SMTP id 69mr1681889lfd.152.1607013876478; Thu, 03 Dec 2020 08:44:36 -0800 (PST) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com. [209.85.208.177]) by smtp.gmail.com with ESMTPSA id d3sm689509lfj.206.2020.12.03.08.44.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Dec 2020 08:44:35 -0800 (PST) Received: by mail-lj1-f177.google.com with SMTP id f24so3208807ljk.13; Thu, 03 Dec 2020 08:44:34 -0800 (PST) X-Received: by 2002:a2e:85ce:: with SMTP id h14mr1596115ljj.190.1607013874724; Thu, 03 Dec 2020 08:44:34 -0800 (PST) MIME-Version: 1.0 References: <20201116125617.7597-1-m.cerveny@computer.org> <20201116125617.7597-4-m.cerveny@computer.org> In-Reply-To: From: Chen-Yu Tsai Date: Fri, 4 Dec 2020 00:44:21 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control To: Martin Cerveny Cc: Maxime Ripard , devel@driverdev.osuosl.org, devicetree , Jernej Skrabec , Mauro Carvalho Chehab , Greg Kroah-Hartman , linux-kernel , Rob Herring , Paul Kocialkowski , Mark Brown , Linux Media Mailing List , Lee Jones , linux-arm-kernel , Icenowy Zheng Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 4, 2020 at 12:25 AM Martin Cerveny wrote: > > Hello. > > On Thu, 3 Dec 2020, Chen-Yu Tsai wrote: > > > Hi, > > > > On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny wrote: > >> > >> Allwinner V3s has system control and SRAM C1 region similar to H3. > >> > >> Signed-off-by: Martin Cerveny > >> --- > >> arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ > >> 1 file changed, 14 insertions(+) > >> > >> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > >> index 0c7341676921..70193512c222 100644 > >> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > >> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > >> @@ -161,6 +161,20 @@ syscon: system-control@1c00000 { > >> #address-cells = <1>; > >> #size-cells = <1>; > >> ranges; > >> + > >> + sram_c: sram@1d00000 { > >> + compatible = "mmio-sram"; > >> + reg = <0x01d00000 0x80000>; > > > > How was this address derived? Did you check that there is actually SRAM here? > > Yes, I did some checking (mmap). But I repeated measurement and found > mirrored regions: > > - SRAM_C is mirrored from 0x0000_4000 (primary location) to 0x01d0_4000 (size 0xb000) > (probably exact size is 0xb0c0) > - rest of 0x01d0_0000 are discontinuously filled with R/W register sets > (probably some internals registers from VE) that I thought to be SRAM too > - register SRAM_CTRL_REG0==0x01c00_0000 (value 0x7fff_ffff) switch whole > region 0x01d0_0000-0x01df_ffff __AND__ 0x0000_4000-0x0000_ffff > - VE/cedrus code use this regions indirectly > (VE_AVC_SRAM_PORT_OFFSET/VE_AVC_SRAM_PORT_DATA...) > and it is not influenced by "true" SRAM mapping or size Could you add this to your commit log? That would make the information available to others, and you could mention that you only added the location that is contiguous SRAM without the interspersed registers. So based on this, and what we've seen with the H616, I'm guessing 0x01d0_0000 - 0x01df_ffff exposes all the internal guts of the VE, while SRAM C @ 0x4000 just maps a small portion out. > -> so I suppose to better use only SRAM_C lower definition: Yes that would be more appropriate, as it matches the manual, and as you mentioned, is *real* SRAM. > --- > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > index e8f304125e2d..90d703e5b73b 100644 > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > @@ -162,17 +162,17 @@ syscon: system-control@1c00000 { > #size-cells = <1>; > ranges; > > - sram_c: sram@1d00000 { > + sram_c: sram@4000 { > compatible = "mmio-sram"; > - reg = <0x01d00000 0x80000>; > + reg = <0x4000 0xb000>; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0 0x01d00000 0x80000>; > + ranges = <0 0 0x4000 0xb000>; > > ve_sram: sram-section@0 { > compatible = "allwinner,sun8i-v3s-sram-c1", > "allwinner,sun4i-a10-sram-c1"; > - reg = <0x000000 0x80000>; > + reg = <0x0 0xb000>; > }; > }; > }; > --- > > Does someone have accessible specific documentation of VE/cedrus for V3s ? I doubt such information exists. Regards ChenYu > Regards, Martin > > > ChenYu > > > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + ranges = <0 0x01d00000 0x80000>; > >> + > >> + ve_sram: sram-section@0 { > >> + compatible = "allwinner,sun8i-v3s-sram-c1", > >> + "allwinner,sun4i-a10-sram-c1"; > >> + reg = <0x000000 0x80000>; > >> + }; > >> + }; > >> }; > >> > >> tcon0: lcd-controller@1c0c000 { > >> -- > >> 2.25.1 > >> > >> > >> _______________________________________________ > >> linux-arm-kernel mailing list > >> linux-arm-kernel@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCCDFC433FE for ; Thu, 3 Dec 2020 16:45:15 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D952320754 for ; Thu, 3 Dec 2020 16:45:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D952320754 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=driverdev-devel-bounces@linuxdriverproject.org Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 4E830871AD; Thu, 3 Dec 2020 16:45:14 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 566YqQT46qZx; Thu, 3 Dec 2020 16:45:13 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by fraxinus.osuosl.org (Postfix) with ESMTP id 36C6986FE6; Thu, 3 Dec 2020 16:45:13 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by ash.osuosl.org (Postfix) with ESMTP id DCA9A1BF2CA for ; Thu, 3 Dec 2020 16:44:39 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id BF86A20477 for ; Thu, 3 Dec 2020 16:44:39 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Wyh5UQiiaoHH for ; Thu, 3 Dec 2020 16:44:38 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mail-lj1-f195.google.com (mail-lj1-f195.google.com [209.85.208.195]) by silver.osuosl.org (Postfix) with ESMTPS id 149612046C for ; Thu, 3 Dec 2020 16:44:38 +0000 (UTC) Received: by mail-lj1-f195.google.com with SMTP id f24so3208889ljk.13 for ; Thu, 03 Dec 2020 08:44:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gSKKMnPPwvy/Gv2/NSqLNOEr9O1XfSpR38BNRVeZqQg=; b=Q03Em/9Lv0Lm4r+Cjj9gCVeS9J7u8FGmcWu7O6/KdJTU/tuKb5PqhdMItT2spkHWC/ u7E6kWUrXPr9G4nQjDx0zSbP8IFwXk7Lz7NXszKHy29eR/2hmPtG2FRqi/ui34lBc4Ko 8fOPBrmCf94Yz9zHL8xlF7cjmAgHtsGnNRBDADYZnOoB9jD+tvqd/CzaIDXP/ROZXytc TFe2lp59JXrnihr2fu2k6+/vQXlfOCPW6HraCt2bBeEPXcAEsMK50CLVRzxyaylYvY1M 4NCfH0A0h2Ii+FTCJdIgl7+JjSJdOoCKbN5kCjdFKK/5sdMsSF02BcIvUv5uITy+Zqm2 vrUQ== X-Gm-Message-State: AOAM532xdUQPDrXILZOtfzbyJhq8rac3Em1JHORiYaoSx45BZG8epPux bilZlW3DZAuXj6tap0P0V4GbDx5CmIYnuQ== X-Google-Smtp-Source: ABdhPJyEyyTdfJUxgb5ZwktBp56ROw/NH6zHDHRcXatqAjAB9ymZ9jSiQ4DgtH9f0K7ggOBNvYmzsA== X-Received: by 2002:a2e:9b8c:: with SMTP id z12mr1520343lji.360.1607013875682; Thu, 03 Dec 2020 08:44:35 -0800 (PST) Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com. [209.85.208.171]) by smtp.gmail.com with ESMTPSA id d19sm686114lfm.211.2020.12.03.08.44.34 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Dec 2020 08:44:35 -0800 (PST) Received: by mail-lj1-f171.google.com with SMTP id y16so3279466ljk.1 for ; Thu, 03 Dec 2020 08:44:34 -0800 (PST) X-Received: by 2002:a2e:85ce:: with SMTP id h14mr1596115ljj.190.1607013874724; Thu, 03 Dec 2020 08:44:34 -0800 (PST) MIME-Version: 1.0 References: <20201116125617.7597-1-m.cerveny@computer.org> <20201116125617.7597-4-m.cerveny@computer.org> In-Reply-To: From: Chen-Yu Tsai Date: Fri, 4 Dec 2020 00:44:21 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control To: Martin Cerveny X-BeenThere: driverdev-devel@linuxdriverproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux Driver Project Developer List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree , Jernej Skrabec , Greg Kroah-Hartman , Mark Brown , linux-kernel , Maxime Ripard , Paul Kocialkowski , Rob Herring , Icenowy Zheng , Mauro Carvalho Chehab , Lee Jones , linux-arm-kernel , Linux Media Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: driverdev-devel-bounces@linuxdriverproject.org Sender: "devel" On Fri, Dec 4, 2020 at 12:25 AM Martin Cerveny wrote: > > Hello. > > On Thu, 3 Dec 2020, Chen-Yu Tsai wrote: > > > Hi, > > > > On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny wrote: > >> > >> Allwinner V3s has system control and SRAM C1 region similar to H3. > >> > >> Signed-off-by: Martin Cerveny > >> --- > >> arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ > >> 1 file changed, 14 insertions(+) > >> > >> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > >> index 0c7341676921..70193512c222 100644 > >> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > >> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > >> @@ -161,6 +161,20 @@ syscon: system-control@1c00000 { > >> #address-cells = <1>; > >> #size-cells = <1>; > >> ranges; > >> + > >> + sram_c: sram@1d00000 { > >> + compatible = "mmio-sram"; > >> + reg = <0x01d00000 0x80000>; > > > > How was this address derived? Did you check that there is actually SRAM here? > > Yes, I did some checking (mmap). But I repeated measurement and found > mirrored regions: > > - SRAM_C is mirrored from 0x0000_4000 (primary location) to 0x01d0_4000 (size 0xb000) > (probably exact size is 0xb0c0) > - rest of 0x01d0_0000 are discontinuously filled with R/W register sets > (probably some internals registers from VE) that I thought to be SRAM too > - register SRAM_CTRL_REG0==0x01c00_0000 (value 0x7fff_ffff) switch whole > region 0x01d0_0000-0x01df_ffff __AND__ 0x0000_4000-0x0000_ffff > - VE/cedrus code use this regions indirectly > (VE_AVC_SRAM_PORT_OFFSET/VE_AVC_SRAM_PORT_DATA...) > and it is not influenced by "true" SRAM mapping or size Could you add this to your commit log? That would make the information available to others, and you could mention that you only added the location that is contiguous SRAM without the interspersed registers. So based on this, and what we've seen with the H616, I'm guessing 0x01d0_0000 - 0x01df_ffff exposes all the internal guts of the VE, while SRAM C @ 0x4000 just maps a small portion out. > -> so I suppose to better use only SRAM_C lower definition: Yes that would be more appropriate, as it matches the manual, and as you mentioned, is *real* SRAM. > --- > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > index e8f304125e2d..90d703e5b73b 100644 > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > @@ -162,17 +162,17 @@ syscon: system-control@1c00000 { > #size-cells = <1>; > ranges; > > - sram_c: sram@1d00000 { > + sram_c: sram@4000 { > compatible = "mmio-sram"; > - reg = <0x01d00000 0x80000>; > + reg = <0x4000 0xb000>; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0 0x01d00000 0x80000>; > + ranges = <0 0 0x4000 0xb000>; > > ve_sram: sram-section@0 { > compatible = "allwinner,sun8i-v3s-sram-c1", > "allwinner,sun4i-a10-sram-c1"; > - reg = <0x000000 0x80000>; > + reg = <0x0 0xb000>; > }; > }; > }; > --- > > Does someone have accessible specific documentation of VE/cedrus for V3s ? I doubt such information exists. Regards ChenYu > Regards, Martin > > > ChenYu > > > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + ranges = <0 0x01d00000 0x80000>; > >> + > >> + ve_sram: sram-section@0 { > >> + compatible = "allwinner,sun8i-v3s-sram-c1", > >> + "allwinner,sun4i-a10-sram-c1"; > >> + reg = <0x000000 0x80000>; > >> + }; > >> + }; > >> }; > >> > >> tcon0: lcd-controller@1c0c000 { > >> -- > >> 2.25.1 > >> > >> > >> _______________________________________________ > >> linux-arm-kernel mailing list > >> linux-arm-kernel@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA0C7C4361A for ; Thu, 3 Dec 2020 16:46:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09D13207AC for ; Thu, 3 Dec 2020 16:46:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 09D13207AC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:In-Reply-To: References:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XmTsX65eDjyi+HkksKdlvsWZAtKL5NojOaGKBuOtJUk=; b=VedgvBtB/OypApE6bmikKPcdJ FSg00/nvRellxpjWsfMPSoBBy5hsDkQquO09GGTK5dfLe0wiZrv6RpuuuUtFCfN7ijDVOPWM3T0Oa tHMUrxoiHd8LKtwUOQ3oIhyPN4PLB1ncj0O2Dk6LLCN3HVa6sYGd53txs6dRn5f9nr5clqvbUNNLJ 8+XFSZGdui3aZy4l9MzZTsEbbrQEF7scPyehDfpnjimvUYGerZvvStqfYIQcIRLcYyqKVIFrjkZn6 reuamZYzOZW4yamx2VHgfMnm/3CB57Sm6R+lDoPH/856m6KAV9PBxVl03ZsvQKsPUQALqasnbsdHc NC4TVQsHw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kkrii-00013k-Qh; Thu, 03 Dec 2020 16:44:40 +0000 Received: from mail-lj1-f196.google.com ([209.85.208.196]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kkrig-00013G-PE for linux-arm-kernel@lists.infradead.org; Thu, 03 Dec 2020 16:44:39 +0000 Received: by mail-lj1-f196.google.com with SMTP id a1so1922454ljq.3 for ; Thu, 03 Dec 2020 08:44:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gSKKMnPPwvy/Gv2/NSqLNOEr9O1XfSpR38BNRVeZqQg=; b=Co+0upZpTl9PjSTh/ig9bX+cXGXN3BFlvD9h66Duz5bz9TADGX1VqZYNRoXDAMMc7s RffyMMoexOja/BvRQR95b1HwnDCuxbRM/PI8ISFDsrQjQAXubJaM+VCFoOyCut62HGKH VtujFjEEiNaeChrN7/UQ+AWkTPi4Oqtcfm/4eWa4IunLv+TQ30KsFcoEiimOr5XnkhDh 73sjJkFBfPO/0AfAxSd2LgY9ccc4wi/aVOQnyurrb8pYIg8LAHdcZZqKM9dfW/VB1vBo wPwG/diQW5styRiDj2OSJWtkcSKcSzJhpGAAHiz3JWuTxU9k/bzUEFHvItNOZw8SpUOi dTWQ== X-Gm-Message-State: AOAM532TJUn3gjIYUsvia1okogWiyAIM5frKjmr1L63QQqjZ1Ei2yQUJ pCwGyUq4Tsu6tLRXKrTsiipfBq51G+YRPA== X-Google-Smtp-Source: ABdhPJzG2RoHKp1q+Qrr/dk8Gond0KmampK6ZCX5NtO4XvCJqxjmWsHgZReox5xxKcTow263TQqDCQ== X-Received: by 2002:a2e:5750:: with SMTP id r16mr1522647ljd.61.1607013876209; Thu, 03 Dec 2020 08:44:36 -0800 (PST) Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com. [209.85.208.172]) by smtp.gmail.com with ESMTPSA id i8sm692147lfl.269.2020.12.03.08.44.34 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Dec 2020 08:44:35 -0800 (PST) Received: by mail-lj1-f172.google.com with SMTP id q8so3219938ljc.12 for ; Thu, 03 Dec 2020 08:44:34 -0800 (PST) X-Received: by 2002:a2e:85ce:: with SMTP id h14mr1596115ljj.190.1607013874724; Thu, 03 Dec 2020 08:44:34 -0800 (PST) MIME-Version: 1.0 References: <20201116125617.7597-1-m.cerveny@computer.org> <20201116125617.7597-4-m.cerveny@computer.org> In-Reply-To: From: Chen-Yu Tsai Date: Fri, 4 Dec 2020 00:44:21 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control To: Martin Cerveny X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201203_114438_851715_52BBCB16 X-CRM114-Status: GOOD ( 27.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree , Jernej Skrabec , Greg Kroah-Hartman , Mark Brown , linux-kernel , Maxime Ripard , Paul Kocialkowski , Rob Herring , Icenowy Zheng , Mauro Carvalho Chehab , Lee Jones , linux-arm-kernel , Linux Media Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 4, 2020 at 12:25 AM Martin Cerveny wrote: > > Hello. > > On Thu, 3 Dec 2020, Chen-Yu Tsai wrote: > > > Hi, > > > > On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny wrote: > >> > >> Allwinner V3s has system control and SRAM C1 region similar to H3. > >> > >> Signed-off-by: Martin Cerveny > >> --- > >> arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ > >> 1 file changed, 14 insertions(+) > >> > >> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > >> index 0c7341676921..70193512c222 100644 > >> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > >> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > >> @@ -161,6 +161,20 @@ syscon: system-control@1c00000 { > >> #address-cells = <1>; > >> #size-cells = <1>; > >> ranges; > >> + > >> + sram_c: sram@1d00000 { > >> + compatible = "mmio-sram"; > >> + reg = <0x01d00000 0x80000>; > > > > How was this address derived? Did you check that there is actually SRAM here? > > Yes, I did some checking (mmap). But I repeated measurement and found > mirrored regions: > > - SRAM_C is mirrored from 0x0000_4000 (primary location) to 0x01d0_4000 (size 0xb000) > (probably exact size is 0xb0c0) > - rest of 0x01d0_0000 are discontinuously filled with R/W register sets > (probably some internals registers from VE) that I thought to be SRAM too > - register SRAM_CTRL_REG0==0x01c00_0000 (value 0x7fff_ffff) switch whole > region 0x01d0_0000-0x01df_ffff __AND__ 0x0000_4000-0x0000_ffff > - VE/cedrus code use this regions indirectly > (VE_AVC_SRAM_PORT_OFFSET/VE_AVC_SRAM_PORT_DATA...) > and it is not influenced by "true" SRAM mapping or size Could you add this to your commit log? That would make the information available to others, and you could mention that you only added the location that is contiguous SRAM without the interspersed registers. So based on this, and what we've seen with the H616, I'm guessing 0x01d0_0000 - 0x01df_ffff exposes all the internal guts of the VE, while SRAM C @ 0x4000 just maps a small portion out. > -> so I suppose to better use only SRAM_C lower definition: Yes that would be more appropriate, as it matches the manual, and as you mentioned, is *real* SRAM. > --- > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > index e8f304125e2d..90d703e5b73b 100644 > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > @@ -162,17 +162,17 @@ syscon: system-control@1c00000 { > #size-cells = <1>; > ranges; > > - sram_c: sram@1d00000 { > + sram_c: sram@4000 { > compatible = "mmio-sram"; > - reg = <0x01d00000 0x80000>; > + reg = <0x4000 0xb000>; > #address-cells = <1>; > #size-cells = <1>; > - ranges = <0 0x01d00000 0x80000>; > + ranges = <0 0 0x4000 0xb000>; > > ve_sram: sram-section@0 { > compatible = "allwinner,sun8i-v3s-sram-c1", > "allwinner,sun4i-a10-sram-c1"; > - reg = <0x000000 0x80000>; > + reg = <0x0 0xb000>; > }; > }; > }; > --- > > Does someone have accessible specific documentation of VE/cedrus for V3s ? I doubt such information exists. Regards ChenYu > Regards, Martin > > > ChenYu > > > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + ranges = <0 0x01d00000 0x80000>; > >> + > >> + ve_sram: sram-section@0 { > >> + compatible = "allwinner,sun8i-v3s-sram-c1", > >> + "allwinner,sun4i-a10-sram-c1"; > >> + reg = <0x000000 0x80000>; > >> + }; > >> + }; > >> }; > >> > >> tcon0: lcd-controller@1c0c000 { > >> -- > >> 2.25.1 > >> > >> > >> _______________________________________________ > >> linux-arm-kernel mailing list > >> linux-arm-kernel@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel