From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DBA1C43144 for ; Thu, 28 Jun 2018 02:24:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C29D2241AA for ; Thu, 28 Jun 2018 02:24:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C29D2241AA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753154AbeF1CY2 (ORCPT ); Wed, 27 Jun 2018 22:24:28 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:41811 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752179AbeF1CY0 (ORCPT ); Wed, 27 Jun 2018 22:24:26 -0400 Received: by mail-ed1-f68.google.com with SMTP id b12-v6so4191914edt.8; Wed, 27 Jun 2018 19:24:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=izbwCorAaW3BZilV+Ue9DofoTlIwRvxm+PcZ0LJFPDw=; b=rtz0TxP23b5CPGFszwYcmVqudhsq4MS7KvZwwmy6kGFroHf2WiHbyFMXLr2baBev8R 2kyZrvn9GmBh9+EsR/ZXuVYSAXFKqjVerOEpWpmWu2p97Sa7zovFRkuWacqwkpPWwJmL pINK7L4oHUbRkk3s/sWm2A9eM2OHWgLYSQk+ulQIYaGspyyxbPGe3PHQR1f1KG1KPQzr pnAucs9AdqIAX2OU4MTGuAzwvBLG0oAuyGEKwm/m9BpKqypBynTw/D0bMwxczX7ZlZ6k 0KnZjrcg+kJLsyAxuFCJvTqRc0Lzt47Z7BGf6Cc7AGUy5B5OzaW1OA/9WoLM/AbonEbz 1svw== X-Gm-Message-State: APt69E3Caw+W6pcYCtmAIu6b3etkuEQTwn/qSFLW2WDCq226Wgf6F2YZ xOHfKvPWnMNzz62KhPgQVvbih3OQ X-Google-Smtp-Source: AAOMgpeUILYZu6FG4IRHx27zqvodR3GdF18M4kjvjWu0T9iMUOPNm7LQGol6CWcg8DUwPAUNVWK2Cw== X-Received: by 2002:a50:c313:: with SMTP id a19-v6mr5242597edb.177.1530152664575; Wed, 27 Jun 2018 19:24:24 -0700 (PDT) Received: from mail-wr0-f169.google.com (mail-wr0-f169.google.com. [209.85.128.169]) by smtp.gmail.com with ESMTPSA id j24-v6sm221272edr.90.2018.06.27.19.24.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jun 2018 19:24:23 -0700 (PDT) Received: by mail-wr0-f169.google.com with SMTP id e18-v6so3838779wrs.5; Wed, 27 Jun 2018 19:24:23 -0700 (PDT) X-Received: by 2002:adf:a54d:: with SMTP id j13-v6mr7424927wrb.155.1530152663063; Wed, 27 Jun 2018 19:24:23 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:adf:a15a:0:0:0:0:0 with HTTP; Wed, 27 Jun 2018 19:24:02 -0700 (PDT) In-Reply-To: <20180625120304.7543-18-jernej.skrabec@siol.net> References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-18-jernej.skrabec@siol.net> From: Chen-Yu Tsai Date: Thu, 28 Jun 2018 10:24:02 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 17/24] drm/sun4i: Don't change clock bits in DW HDMI PHY driver To: Jernej Skrabec Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote: > DW HDMI PHY driver and PHY clock driver share same registers. Make sure > that DW HDMI PHY setup code doesn't change any clock related bits. > During initialization, set PHY PLL parent bit to 0. > > Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai and maybe a fixes tag? From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCH v3 17/24] drm/sun4i: Don't change clock bits in DW HDMI PHY driver Date: Thu, 28 Jun 2018 10:24:02 +0800 Message-ID: References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-18-jernej.skrabec@siol.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180625120304.7543-18-jernej.skrabec@siol.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jernej Skrabec Cc: Mark Rutland , devicetree , Maxime Ripard , linux-kernel , dri-devel , David Airlie , linux-sunxi , Rob Herring , linux-clk , linux-arm-kernel List-Id: devicetree@vger.kernel.org T24gTW9uLCBKdW4gMjUsIDIwMTggYXQgODowMiBQTSwgSmVybmVqIFNrcmFiZWMgPGplcm5lai5z a3JhYmVjQHNpb2wubmV0PiB3cm90ZToKPiBEVyBIRE1JIFBIWSBkcml2ZXIgYW5kIFBIWSBjbG9j ayBkcml2ZXIgc2hhcmUgc2FtZSByZWdpc3RlcnMuIE1ha2Ugc3VyZQo+IHRoYXQgRFcgSERNSSBQ SFkgc2V0dXAgY29kZSBkb2Vzbid0IGNoYW5nZSBhbnkgY2xvY2sgcmVsYXRlZCBiaXRzLgo+IER1 cmluZyBpbml0aWFsaXphdGlvbiwgc2V0IFBIWSBQTEwgcGFyZW50IGJpdCB0byAwLgo+Cj4gU2ln bmVkLW9mZi1ieTogSmVybmVqIFNrcmFiZWMgPGplcm5lai5za3JhYmVjQHNpb2wubmV0PgoKUmV2 aWV3ZWQtYnk6IENoZW4tWXUgVHNhaSA8d2Vuc0Bjc2llLm9yZz4KCmFuZCBtYXliZSBhIGZpeGVz IHRhZz8KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJp LWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Thu, 28 Jun 2018 10:24:02 +0800 Subject: [PATCH v3 17/24] drm/sun4i: Don't change clock bits in DW HDMI PHY driver In-Reply-To: <20180625120304.7543-18-jernej.skrabec@siol.net> References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-18-jernej.skrabec@siol.net> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote: > DW HDMI PHY driver and PHY clock driver share same registers. Make sure > that DW HDMI PHY setup code doesn't change any clock related bits. > During initialization, set PHY PLL parent bit to 0. > > Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai and maybe a fixes tag?