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[74.125.82.43]) by smtp.gmail.com with ESMTPSA id x15-v6sm855009edd.90.2018.06.12.20.19.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Jun 2018 20:19:06 -0700 (PDT) Received: by mail-wm0-f43.google.com with SMTP id r15-v6so2118195wmc.1; Tue, 12 Jun 2018 20:19:06 -0700 (PDT) X-Received: by 2002:a1c:bf0c:: with SMTP id p12-v6mr2079024wmf.120.1528859946259; Tue, 12 Jun 2018 20:19:06 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:adf:a158:0:0:0:0:0 with HTTP; Tue, 12 Jun 2018 20:18:45 -0700 (PDT) In-Reply-To: <20180612200036.21483-2-jernej.skrabec@siol.net> References: <20180612200036.21483-1-jernej.skrabec@siol.net> <20180612200036.21483-2-jernej.skrabec@siol.net> From: Chen-Yu Tsai Date: Wed, 13 Jun 2018 11:18:45 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs To: Jernej Skrabec Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 13, 2018 at 4:00 AM, Jernej Skrabec wrote: > According to documentation and experience with other similar SoCs, video > PLLs don't work stable if their output frequency is set below 192 MHz. > > Because of that, set minimal rate to both R40 video PLLs to 192 MHz. > > Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs Date: Wed, 13 Jun 2018 11:18:45 +0800 Message-ID: References: <20180612200036.21483-1-jernej.skrabec@siol.net> <20180612200036.21483-2-jernej.skrabec@siol.net> Reply-To: wens-jdAy2FN1RRM@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20180612200036.21483-2-jernej.skrabec-gGgVlfcn5nU@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Jernej Skrabec Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi List-Id: devicetree@vger.kernel.org On Wed, Jun 13, 2018 at 4:00 AM, Jernej Skrabec wrote: > According to documentation and experience with other similar SoCs, video > PLLs don't work stable if their output frequency is set below 192 MHz. > > Because of that, set minimal rate to both R40 video PLLs to 192 MHz. > > Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Wed, 13 Jun 2018 11:18:45 +0800 Subject: [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs In-Reply-To: <20180612200036.21483-2-jernej.skrabec@siol.net> References: <20180612200036.21483-1-jernej.skrabec@siol.net> <20180612200036.21483-2-jernej.skrabec@siol.net> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Jun 13, 2018 at 4:00 AM, Jernej Skrabec wrote: > According to documentation and experience with other similar SoCs, video > PLLs don't work stable if their output frequency is set below 192 MHz. > > Because of that, set minimal rate to both R40 video PLLs to 192 MHz. > > Signed-off-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai